 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| november 1998 general description features lxt974a/lxt975a fast ethernet 10/100 quad transceivers lxt974a/975a block diagram revision 1.3 data sheet global functions tristate control decoder & descrambler rxdn<3:0> tpon/fibip n tpop/fibin n + - + - tpin/fibon n tpip/fibop n + - tp rcvr + - ecl rcvr serial to parallel converter scrambler & encoder txd n <3:0> parallel/serial converter tx_er n tx_en n carrier sense collision detect data valid error detect col n crs n rx_er n rx_dv n rx_clk n fdx status & led drivers trste n led n <2:0> 3 clock generator auto negotiation baseline wander correction pwr supply / pwrdown pwrdn slicer manchester decoder pulse shaper manchester encoder 10 100 10 100 internal clocks clk25m media select & line energy monitor port 0 port 1 port 2 port 3 vcc gnd management / mode select logic mii mii serled per-port functions tp driver ecl driver tp out / fiber in fiber out / tp in 3 tx_clk n sd/tx n register set reset ledena ledclk leddat mii_md<1:0> addr<4:2> mdio mdc cfg<2:0> mdint vccmii mii power supply 3.3v or 5v the lxt974a and lxt975a are four-port phy fast ethernet transceivers which support ieee 802.3 physical layer applications at both 10 mbps and 100 mbps. they provide all of the active circuitry to interface four 802.3 media independent interface (mii) compliant controllers to 10base-t and/or 100base-tx media. this data sheet applies to all lxt974_ and lxt975_ products including lxt974, lxt975 and any subsequent variants, except as specifically noted. all four ports on the lxt974a provide a combination twisted-pair (tp) or pseudo-ecl (pecl) interface for a 10/100base-tx or 100base-fx connection. the lxt975a is pin compatible with the lxt974a except for the network ports. the lxt975a is optimized for dual- high stacked rj45 modular applications and provides a twisted-pair interface on every port, but the pecl interface on only two. the lxt974a/975a provides three separate led drivers for each of the four phy ports and a serial led interface. in addition to standard ethernet, each chip supports full- duplex operation at 10 mbps and 100 mbps. the lxt974a/975a requires only a single 5v power supply. the mii may be operated independently with either a 3.3v or 5v supply. ? four independent ieee 802.3-compliant 10base-t or 100base-tx ports in a single chip. ? 100base-fx fiber-optic capable. ? standard csma/cd or full-duplex operation. ? supports auto-negotiation and legacy systems without auto-negotiation capability. ? baseline wander correction. ? 100base-tx line performance over 130 meters. ? configurable led drivers and serial led output. ? configurable through mii serial port or via external control pins. ? available in 160-pin pqfp with heat spreader. ? commercial temperature range (0-70 o c ambient). ?part numbers: ? lxt974ahc (new designation) ? LXT974QC (original designation) ? lxt975ahc (new designation) ? lxt975qc (original designation) applications ? 10base-t, 10/100-tx, or 100base-fx switches and multi-port nics. ? lxt975a optimized for dual-high stacked modular rj45 applications. refer to www.level1.com for current product information.
lxt974a/lxt975a fast ethernet 10/100 quad transceiver 2 table of contents pin assignments and signal descriptions ................................................................... 4 functional description ..................................................................................................... 14 introduction ................................................................................................................... ........... 14 network media/protocol support ............................................................................................. 15 10/100 mbps network interface.......................................................................................... 15 twisted-pair interface.................................................................................................... 15 fiber interface ............................................................................................................... 1 5 mii interface.................................................................................................................. ...... 16 mii data interface .......................................................................................................... 16 loopback ....................................................................................................................... 17 mii management interface............................................................................................. 18 mii interrupts ....................................................................................................... 18 hardware control interface................................................................................................. 19 initialization ................................................................................................................. ............. 21 mdio control mode............................................................................................................ 21 manual control mode ......................................................................................................... 21 link configuration............................................................................................................. .. 21 auto-negotiation ............................................................................................................... ....... 22 100 mbps operation ............................................................................................................. ... 23 4b/5b coding table ............................................................................................................ 2 4 100base-x protocol sublayer operations......................................................................... 25 10 mbps operation .............................................................................................................. .... 28 led functions .................................................................................................................. ....... 29 serial led output.............................................................................................................. .29 per-port leds.................................................................................................................. ... 29 operating requirements......................................................................................................... .30 power requirements .......................................................................................................... 30 clock requirements ........................................................................................................... 30 application information ................................................................................................... 31 design recommendations....................................................................................................... 31 power supply filtering........................................................................................................ 3 1 power and ground plane layout considerations............................................................... 32 twisted-pair and fiber interfaces ....................................................................................... 33 magnetics information ........................................................................................................ 34 magnetics with improved return loss performance .................................................... 34 typical application circuitry .................................................................................................. ... 36 3 lxt974a/lxt975a table of contents test specifications ............................................................................................................ .. 42 absolute maximum ratings ................................................................................................ 42 operating conditions .......................................................................................................... 4 2 digital i/o characteristics.................................................................................................... 43 digital i/o characteristics - mii pins ................................................................................... 43 required clk25m characteristics ...................................................................................... 43 low-voltage fault detect characteristics ........................................................................... 44 100base-tx transceiver characteristics .......................................................................... 44 100base-fx transceiver characteristics .......................................................................... 45 10base-t transceiver characteristics............................................................................... 45 mii-100base-tx receive timing ...................................................................................... 46 mii-100base-tx transmit timing ..................................................................................... 47 mii-100base-fx receive timing ....................................................................................... 48 mii-100base-fx transmit timing ...................................................................................... 49 mii-10base-t receive timing ........................................................................................... 50 mii-10base-t transmit timing........................................................................................... 51 10base-t sqe (heartbeat) timing.................................................................................... 52 10base-t jab and unjab timing ....................................................................................... 52 auto negotiation and fast link pulse timing ..................................................................... 53 mdio and mii timing .......................................................................................................... 54 reset and power-down recovery timing .......................................................................... 55 serial led timing .............................................................................................................. .55 register definitions ........................................................................................................... .56 control register (address 0)............................................................................................... 57 status register (address 1) ................................................................................................ 58 phy identification register 1 (address 2)........................................................................... 59 phy identification register 2 (address 3)........................................................................... 59 auto negotiation advertisement register (address 4)........................................................ 60 auto negotiation link partner ability register (address 5)................................................. 61 auto negotiation expansion (address 6) ............................................................................ 62 led configuration register (address 16, hex 10) .............................................................. 63 interrupt enable register (address 17, hex 11) .................................................................. 64 interrupt status register (address 18, hex 12) ................................................................... 64 port configuration register (address 19, hex 13) .............................................................. 65 port status register (address 20, hex 14).......................................................................... 66 package specification........................................................................................................ 67 revision history ............................................................................................................... ..... 68 lxt974a/lxt975a fast ethernet 10/100 quad transceiver 4 pin assignments and signal descriptions figure 1: lxt974 pin assignments xxxx xxxx lxt974ahc or LXT974QC xxxxxx (date code) (part#) led3_0 ..... 1 led3_1 ..... 2 led3_2 ..... 3 led2_0 ..... 4 led2_1 ..... 5 led2_2 ..... 6 gnd ..... 7 led1_0 ..... 8 led1_1 ..... 9 led1_2 ..... 10 led0_0 ..... 11 led0_1 ..... 12 led0_2 ..... 13 gnd ..... 14 ledclk ..... 15 leddat ..... 16 ledena ..... 17 add2 ..... 18 add3 ..... 19 add4 ..... 20 gnda ..... 21 vcc ..... 22 rxd0_3 ..... 23 rxd0_2 ..... 24 rxd0_1 ..... 25 rxd0_0 ..... 26 rx_dv0 ..... 27 rx_clk0 ..... 28 rx_er0 ..... 29 tx_er0 ..... 30 tx_clk0 ..... 31 tx_en0 ..... 32 txd0_0 ..... 33 txd0_1 ..... 34 txd0_2 ..... 35 txd0_3 ..... 36 col0 ..... 37 crs0 ..... 38 gnd ..... 39 vccmii ..... 40 120 ........ n/c 119 ........ n/c 118 ........ clk25m 117 ........ fde_fx 116 ........ cfg_0 115 ........ cfg_1 114 ........ cfg_2 113 ........ bypscr 112 ........ test 111 ........ autoena 110 ........ fde 109 ........ reset 108 ........ gndh 107 ........ vcch 106 ........ trste0 105 ........ trste1 104 ........ trste2 103 ........ trste3 102 ........ pwrdn 101 ........ test 100 ........ mddis 99 .......... mdc 98 .......... mdint 97 .......... mdio 96 .......... vcc 95 .......... gnd 94 .......... crs3 93 .......... col3 92 .......... txd3_3 91 .......... txd3_2 90 .......... txd3_1 89 .......... txd3_0 88 .......... tx_en3 87 .......... tx_clk3 86 .......... tx_er3 85 .......... rx_er3 84 .......... rx_clk3 83 .......... rx_dv3 82 .......... rxd3_0 81 .......... rxd3_1 160 ... gnd 159 ... test 158 ... sd0/tp 0 157 ... tpon/fibip0 156 ... vcct 155 ... gndt 154 ... tpop/fibin0 153 ... vccr 152 ... tpin/fibon0 151 ... tpip/fibop0 150 ... gndr 149 ... sd1/tp 1 148 ... tpon/fibip1 147 ... vcct 146 ... gndt 145 ... tpop/fibin1 144 ... vccr 143 ... tpin/fibon1 142 ... tpip/fibop1 141 ... gndr 140 ... rbias 139 ... sd2/tp 2 138 ... tpon/fibip2 137 ... vcct 136 ... gndt 135 ... tpop/fibin2 134 ... vccr 133 ... tpin/fibon2 132 ... tpip/fibop2 131 ... gndr 130 ... sd3/tp 3 129 ... tpon/fibip3 128 ... vcct 127 ... gndt 126 ... tpop/fibin3 125 ... vccr 124 ... tpin/fibon3 123 ... tpip/fibop3 122 ... gndr 121 ... gndr n/c...................41 rxd1_3............42 rxd1_2............43 rxd1_1............44 rxd1_0............45 rx_dv1 ...........46 rx_clk1.........47 rx_er1 ...........48 tx_er1 ...........49 tx_clk1.........50 tx_en1 ...........51 txd1_0............52 txd1_1............53 txd1_2............54 txd1_3............55 gnd.................56 col1................57 crs1 ................58 gnd.................59 vcc..................60 rxd2_3............61 rxd2_2............62 rxd2_1............63 rxd2_0............64 rx_dv2 ...........65 rx_clk2.........66 rx_er2 ...........67 tx_er2 ...........68 tx_clk2.........69 tx_en2 ...........70 txd2_0............71 txd2_1............72 txd2_2............73 txd2_3............74 col2................75 crs2 ................76 gnd.................77 vccmii ...........78 rxd3_3............79 rxd3_2............80 (lot#) 5 lxt974a/lxt975a pin assignments and signal descriptions table 1: lxt974a signal detect/tp select signal descriptions pin# 2 symbol type 1 signal description 158 149 139 130 sd0/tp0 sd1/tp1 sd2/tp2 sd3/tp3 i signal detect - ports 0 - 3 . when sd/tp n pins are tied high or to a 5v pecl input, bit 19.2 = 1 and the operating mode of each respective port is forced to fx mode. in this mode, full-duplex is set via pin 117 (fde_fx). when not using fx mode, sd/ tp n pins should be tied to gndt. tp select - ports 0 - 3 . when sd/tp n pins are tied low, bit 19.2 = 0. the operating mode of each port can be set to 10base-t, 100base-tx, or 100base-fx via the hardware control interface pins as shown in table 8 on page 11. note: hardware control interface pins (cfg_0, cfg_1, cfg_2, fde, bypscr, and autoena) are global and set all ports simultaneously. in tp mode, network pins operate as described in table 2. in fx mode, network pins are re-mapped and operate as described in table 3. 1. type column coding: i = input, o = output. 2. when not using fiber mode, sd/tp n pins should be tied to gndt. table 2: lxt974a twisted-pair interface signal descriptions pin# symbol type 1 signal description 154, 157 145, 148 135, 138 126, 129 tpop0, tpon0 tpop1, tpon1 tpop2, tpon2 tpop3, tpon3 o twisted-pair outputs, positive & negative - ports 0-3. during 100base-tx or 10base-t operation, tpo pins drive 802.3 compliant pulses onto the line. 151, 152 142, 143 132, 133 123, 124 tpip0, tpin0 tpip1, tpin1 tpip2, tpin2 tpip3, tpin3 i twisted-pair inputs, positive & negative - ports 0-3. during 100base-tx or 10base-t operation, tpi pins receive differential 100base-tx or 10base-t signals from the line. 1. type column coding: i = input, o = output. table 3: lxt974a fiber interface signal descriptions pin# symbol type 1 signal description 154, 157 145, 148 135, 138 126, 129 fibin0, fibip0 fibin1, fibip1 fibin2, fibip2 fibin3, fibip3 i fiber inputs, positive & negative - ports 0-3. during 100base-fx operation, fibi pins receive differential pecl inputs from fiber transceivers. 151, 152 142, 143 132, 133 123, 124 fibop0, fibon0 fibop1, fibon1 fibop2, fibon2 fibop3, fibon3 o fiber outputs, positive & negative - ports 0-3. during 100base-fx operation, fibo pins produce differential pecl outputs for fiber transceivers. 1. type column coding: i = input, o = output. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 6 figure 2: lxt975a pin assignments ) xxxx xxxx lxt975ahc or lxt975qc xxxxxx (date code) (part#) (lot#) led3_0 ..... 1 led3_1 ..... 2 led3_2 ..... 3 led2_0 ..... 4 led2_1 ..... 5 led2_2 ..... 6 gnd ..... 7 led1_0 ..... 8 led1_1 ..... 9 led1_2 ..... 10 led0_0 ..... 11 led0_1 ..... 12 led0_2 ..... 13 gnd ..... 14 ledclk ..... 15 leddat ..... 16 ledena ..... 17 add2 ..... 18 add3 ..... 19 add4 ..... 20 gnda ..... 21 vcc ..... 22 rxd0_3 ..... 23 rxd0_2 ..... 24 rxd0_1 ..... 25 rxd0_0 ..... 26 rx_dv0 ..... 27 rx_clk0 ..... 28 rx_er0 ..... 29 tx_er0 ..... 30 tx_clk0 ..... 31 tx_en0 ..... 32 txd0_0 ..... 33 txd0_1 ..... 34 txd0_2 ..... 35 txd0_3 ..... 36 col0 ..... 37 crs0 ..... 38 gnd ..... 39 vccmii ..... 40 120 ........ n/c 119 ........ n/c 118 ........ clk25m 117 ........ fde_fx 116 ........ cfg_0 115 ........ cfg_1 114 ........ cfg_2 113 ........ bypscr 112 ........ test 111 ........ autoena 110 ........ fde 109 ........ reset 108 ........ gndh 107 ........ vcch 106 ........ trste0 105 ........ trste1 104 ........ trste2 103 ........ trste3 102 ........ pwrdn 101 ........ test 100 ........ mddis 99 .......... mdc 98 .......... mdint 97 .......... mdio 96 .......... vcc 95 .......... gnd 94 .......... crs3 93 .......... col3 92 .......... txd3_3 91 .......... txd3_2 90 .......... txd3_1 89 .......... txd3_0 88 .......... tx_en3 87 .......... tx_clk3 86 .......... tx_er3 85 .......... rx_er3 84 .......... rx_clk3 83 .......... rx_dv3 82 .......... rxd3_0 81 .......... rxd3_1 160 ... gnd 159 ... test 158 ... tpip0 157 ... tpin0 156 ... gndr 155 ... tpop0 154 ... vcct 153 ... gndt 152 ... tpon0 151 ... vccr 150 ... gndr 149 ... sd1/tp 1 148 ... tpon/fibip1 147 ... vcct 146 ... gndt 145 ... tpop/fibin1 144 ... vccr 143 ... tpin/fibon1 142 ... tpip/fibop1 141 ... gndr 140 ... rbias 139 ... tpip2 138 ... tpin2 137 ... gndr 136 ... tpop2 135 ... vcct 134 ... gndt 133 ... tpon2 132 ... vccr 131 ... gndr 130 ... sd3/tp 3 129 ... tpon/fibip3 128 ... vcct 127 ... gndt 126 ... tpop/fibin3 125 ... vccr 124 ... tpin/fibon3 123 ... tpip/fibop3 122 ... gndr 121 ... gndr n/c...................41 rxd1_3............42 rxd1_2............43 rxd1_1............44 rxd1_0............45 rx_dv1 ...........46 rx_clk1.........47 rx_er1 ...........48 tx_er1 ...........49 tx_clk1.........50 tx_en1 ...........51 txd1_0............52 txd1_1............53 txd1_2............54 txd1_3............55 gnd.................56 col1................57 crs1 ................58 gnd.................59 vcc..................60 rxd2_3............61 rxd2_2............62 rxd2_1............63 rxd2_0............64 rx_dv2 ...........65 rx_clk2.........66 rx_er2 ...........67 tx_er2 ...........68 tx_clk2.........69 tx_en2 ...........70 txd2_0............71 txd2_1............72 txd2_2............73 txd2_3............74 col2................75 crs2 ................76 gnd.................77 vccmii ...........78 rxd3_3............79 rxd3_2............80 7 lxt974a/lxt975a pin assignments and signal descriptions table 4: lxt975a signal detect/tp select signal descriptions pin# 2 symbol type 1 signal description 149 130 sd1/tp1 sd3/tp3 i signal detect - ports 1 & 3 . when sd/tp n pins are tied high or to a 5v pecl input, bit 19.2 = 1 and the operating mode of each respective port is forced to fx mode. in this mode, full-duplex is set via pin 117 (fde_fx). when not using fiber mode, sd/tp n pins should be tied to gndt. tp select - ports 1 & 3 . when sd/tp n pins are tied low, bit 19.2 = 0. the operating mode of each port can be set to 10base-t, 100base-tx, or 100base- fx via the hardware control interface pins as shown in table 8 on page 11. note: hardware control interface pins (cfg_0, cfg_1, cfg_2, fde, bypscr, and autoena) are global and set all ports simultaneously. in tp mode, network pins operate as described in table 5. in fx mode, network pins are re-mapped and operate as described in table 6. 1. type column coding: i = input, o = output. 2. when not using fiber mode, sd/tp n pins should be tied to gndt. table 5: lxt975a twisted-pair interface signal descriptions pin# symbol type 1 signal description 155, 152 145, 148 136, 133 126, 129 tpop0, tpon0 tpop1, tpon1 tpop2, tpon2 tpop3, tpon3 o twisted-pair outputs, positive & negative - ports 0-3. during 100base-tx or 10base-t operation, tpo pins drive 802.3 compliant pulses onto the line. 158, 157 142, 143 139, 138 123, 124 tpip0, tpin0 tpip1, tpin1 tpip2, tpin2 tpip3, tpin3 i twisted-pair inputs, positive & negative - ports 0-3. during 100base-tx or 10base-t operation, tpi pins receive differential 100base-tx or 10base-t signals from the line. 1. type column coding: i = input, o = output. table 6: lxt975a fiber interface signal descriptions pin# symbol type 1 signal description 145, 148 126, 129 fibin1, fibip1 fibin3, fibip3 i fiber network interface - ports 1 and 3 during 100base-fx operation, fibi pins receive differential pecl inputs from fiber transceivers. 142, 143 123, 124 fibop1, fibon1 fibop3, fibon3 o fiber network interface - ports 1 and 3 during 100base-fx operation, fibo pins produce differential pecl outputs for fiber transceivers. 1. type column coding: i = input, o = output. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 8 table 7: lxt974a and lxt975a mii signal descriptions pin# 3 symbol type 1 signal description 2 mii data interface pins 33 34 35 36 txd0_0 txd0_1 txd0_2 txd0_3 i transmit data - port 0 . inputs containing nrz data to be transmitted from port 0. 52 53 54 55 txd1_0 txd1_1 txd1_2 txd1_3 i transmit data - port 1 . inputs containing nrz data to be transmitted from port 1. 71 72 73 74 txd2_0 txd2_1 txd2_2 txd2_3 i transmit data - port 2 . inputs containing nrz data to be transmitted from port 2. 89 90 91 92 txd3_0 txd3_1 txd3_2 txd3_3 i transmit data - port 3 . inputs containing nrz data to be transmitted from port 3. 32 51 70 88 tx_en0 tx_en1 tx_en2 tx_en3 i transmit enable - ports 0 - 3 . active high input enables respective port transmitter. this signal must be synchronous to the tx_clk. 31 50 69 87 tx_clk0 tx_clk1 tx_clk2 tx_clk3 o transmit clock - ports 0 - 3 . 25 mhz for 100 mbps operation, 2.5 mhz for 10 mbps operation. the transmit data and control signals must always be synchronized to tx_clk by the mac. the lxt974a/975a normally samples these signals on the rising edge of tx_clk. however, advanced tx_clk mode is available by setting mii register bit 19.5=1. in this mode, the lxt974a/975a samples the transmit data and control signals on the falling edge of tx_clk. 30 49 68 86 tx_er0 tx_er1 tx_er2 tx_er3 i transmit coding error - ports 0 - 3 . this signal must be driven synchronously to tx_clk. when high, forces the respective port to transmit halt (h) code group. 1. type column coding: i = input, o = output, od = open drain 2. the lxt974a/975a supports the 802.3 mdio register set. specific bits in the registers are referenced using an x.y notation, where x is the register number (0-6 or 16-20) and y is the bit number (0-15). 3. unused pins should be tied low. 9 lxt974a/lxt975a pin assignments and signal descriptions 26 25 24 23 rxd0_0 rxd0_1 rxd0_2 rxd0_3 o receive data - port 0 . receive data signals (4-bit parallel nibbles) are driven synchronously to rx_clk0. 45 44 43 42 rxd1_0 rxd1_1 rxd1_2 rxd1_3 o receive data - port 1 . receive data signals (4-bit parallel nibbles) are driven synchronously to rx_clk1. 64 63 62 61 rxd2_0 rxd2_1 rxd2_2 rxd2_3 o receive data - port 2 . receive data signals (4-bit parallel nibbles) are driven synchronously to rx_clk2. 82 81 80 79 rxd3_0 rxd3_1 rxd3_2 rxd3_3 o receive data - port 3 . receive data signals (4-bit parallel nibbles) are driven synchronously to rx_clk3. 27 46 65 83 rx_dv0 rx_dv1 rx_dv2 rx_dv3 o receive data valid - ports 0 - 3 . these signals are synchronous to the respective rx_clk n . active high indication that received code group maps to valid data. 29 48 67 85 rx_er0 rx_er1 rx_er2 rx_er3 o receive error - ports 0 - 3 . these signals are synchronous to the respective rx_clk n . active high indicates that received code group is invalid, or that pll is not locked. 28 47 66 84 rx_clk0 rx_clk1 rx_clk2 rx_clk3 o receive clock - ports 0 - 3 . 25 mhz for 100 mbps and 2.5 mhz for 10 mbps. 37 57 75 93 col0 col1 col2 col3 o collision detected - ports 0 - 3 . active high outputs asserted upon detection of a collision. remain high for the duration of the collision. these signals are generated asynchronously. inactive during full-duplex operation. 38 58 76 94 crs0 crs1 crs2 crs3 o carrier sense - ports 0 - 3 . active high signals. during half-duplex operation (bit 0.8 = 0), crs n is asserted when either transmit or receive medium is non-idle. during full-duplex operation (bit 0.8 = 1), crs n is asserted only when the receive medium is non-idle. table 7: lxt974a and lxt975a mii signal descriptions C continued pin# 3 symbol type 1 signal description 2 1. type column coding: i = input, o = output, od = open drain 2. the lxt974a/975a supports the 802.3 mdio register set. specific bits in the registers are referenced using an x.y notation, where x is the register number (0-6 or 16-20) and y is the bit number (0-15). 3. unused pins should be tied low. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 10 mii control interface pins 97 mdio i/o management data input/output . bidirectional serial data channel for phy/sta communication. 98 mdint od management data interrupt . an active low output on this pin indicates status change. interrupt is cleared by sequentially reading register 1, then register 18. 99 mdc i management data clock . clock for the mdio serial data channel. maximum frequency is 2.5 mhz. 100 mddis i management disable . when mddis is high, the mdio is restricted to read only and the hardware control interface pins provide continual control of their respective bits. when mddis is low at power up or reset, the hardware control interface pins control only the initial or default values of their respective register bits. after the power-up/reset cycle is complete, bit control reverts to the mdio serial channel. 106 105 104 103 trste0 trste1 trste2 trste3 i tristate - ports 0 - 3 . this bit controls bit 0.10 (isolate bit). when trste n is high, the respective port isolates itself from the mii data interface. when mddis is high, trste provides continuous control over bit 0.10. when mddis is low, trste sets the initial (default) value of bit 0.10 at reset and then bit control reverts back to the mdio interface. table 7: lxt974a and lxt975a mii signal descriptions C continued pin# 3 symbol type 1 signal description 2 1. type column coding: i = input, o = output, od = open drain 2. the lxt974a/975a supports the 802.3 mdio register set. specific bits in the registers are referenced using an x.y notation, where x is the register number (0-6 or 16-20) and y is the bit number (0-15). 3. unused pins should be tied low. 11 lxt974a/lxt975a pin assignments and signal descriptions table 8: lxt974a and lxt975a hardware control interface signal descriptions pin# symbol type 1 signal description 2 116 cfg_0 (global) i configuration control 0 . when a/n is enabled, low to high transition on cfg_0 causes auto-negotiate to restart on all ports and 0.9 = 1. when a/n is disabled , this input selects operating speed and directly affects bit 0.13. when cfg_0 is high, 100 mbps is selected and bit 0.13 = 1. when cfg_0 is low, 10 mbps is selected and bit 0.13 = 0. 115 cfg_1 (global) i configuration control 1 . when a/n is enabled , cfg_1 determines operating speed advertisement capabilities in combination with cfg_2 and fde on all ports. see table 16 on page 19 for details. when a/n is disabled , cfg_1 enables 10 mbps link test and directly affects bit 19.8. when cfg_1 is high, 10 mbps link test is disabled and bit 19.8 = 1. when cfg_1 is low, 10 mbps link test is enabled and bit 19.8 = 0. 114 cfg_2 (global) i configuration control 2 . when a/n is enabled , cfg_2 determines operating speed advertisement capabilities in combination with cfg_1 on all ports. see table 16 on page 19 for details. when a/n is disabled , this input selects either tp or fx interface. when fx interface is selected, the lxt974a/975a will automatically disable the scrambler. for correct fx operation, 100 mbps operation must also be selected. note: it is recommended to set the network interface for each port independently, via the sd/tp n pins. see tables 1 and 4 for signal detect / tp select signal descriptions and operation. when cfg_2 is low, tp is enabled and bit 19.2 = 0. when cfg_2 is high, fx is enabled and bit 19.2 = 1. 110 fde (global) i full-duplex enable - all ports . when high, enables full-duplex operation on all ports. 117 fde_fx i full-duplex enable - fx ports only . when high, enables full-duplex operation on all ports set for fx mode operation. this pin is ignored on ports set for tp mode. 113 bypscr (global) i bypass scrambler . in tp mode , enables or bypasses scrambler operation and directly affects mdio register bit 19.3. when high, scrambler is bypassed and bit 19.3 = 1. when low, scrambler is enabled and bit 19.3 = 0. in fx mode , the lxt974a/975a_ automatically bypasses the scrambler. this pin has no effect selecting scrambler bypass. 111 autoena (global) i auto-negotiation enable . when high, enables auto-negotiation on all ports. 1. type column coding: i = input, o = output, od = open drain. 2. the lxt974a/975a/975_ supports the 802.3 mdio register set. specific bits in the registers are referenced using an x.y nota tion, where x is the register number (0-6 or 16-20) and y is the bit number (0-15). lxt974a/lxt975a fast ethernet 10/100 quad transceiver 12 table 9: lxt974a and lxt975a miscellaneous signal descriptions pin# symbol type 1 signal description 2 20 19 18 add4 add3 add2 i i i address <4:2> . set upper three bits of phy address. add<1:0> are set internally to match port number as shown at right. add1 add0 port 00 0 01 1 10 2 11 3 101, 112, 159 test i te s t . must be tied low. 140 rbias i bias . this pin provides bias current for the internal circuitry. must be tied to ground through a 22 k w resistor. 118 clk25m i clock input . a 25 mhz clock input is required at this pin. refer to func- tional description for detailed clock requirements. 109 reset i reset . this active low input is ored with the control register reset bit (0.15). the lxt974a/975a reset cycle is extended 205 m s (nominal) after reset is de-asserted. 102 pwrdn i power down . when high, forces lxt974a/975a into power down mode. this pin is ored with the power down bit (0.11). refer to table 44 on page 56 for more information. 41, 119, 120 n/c - no connection . leave open. 1. type column coding: i = input, o = output, a = analog. 2. the lxt974a/975a supports the 802.3 mdio register set. specific bits in the registers are referenced using an x.y notation, where x is the register number (0-6 or 16-20) and y is the bit number (0-15). table 10: lxt974a and lxt975a led indicator signal descriptions pin# 2 symbol type 1 signal description 3 11 8 4 1 led0_0 led1_0 led2_0 led3_0 od led0 - ports 0 - 3 . in default mode, active low output indicates transmitter active. however, led0 is programmable and may also be set to indicate receiver active, link status or duplex status. refer to led configuration register, table 51 on page 62, for details on programming options. 12 9 5 2 led0_1 led1_1 led2_1 led3_1 od led1 - ports 0 - 3 . in default mode, active low output indicates receiver active. however, led1 is programmable and may also be set to indicate link status, duplex status, or operating speed. refer to led configuration register, table 51 on page 62, for details on programming options. 13 10 6 3 led0_2 led1_2 led2_2 led3_2 od led2 - ports 0 - 3 . in default mode, active low output indicates link up. however, led2 is programmable and may also be set to indicate duplex status, operating speed or collision. refer to led configuration register, table 51 on page 62, for details on programming options. 17 ledena o led enable. active high output signals external device that leddat is active. 15 ledclk o led clock. 25 mhz clock for led serial data output. 16 leddat o led data. serial data output for 24 leds (6 x 4 ports) data. 1. type column coding: i = input, o = output, od = open drain. 2. unused pins should be tied low. 3. the lxt974a/975a supports the 802.3 mdio register set. specific bits in the registers are referenced using an x.y notation, where x is the register number (0-6 or 16-20) and y is the bit number (0-15). 13 lxt974a/lxt975a pin assignments and signal descriptions table 11: lxt974a power supply signal descriptions pin# symbol type signal description 22, 60, 96 vcc - power supply. +5v supply for all digital circuits. 40, 78 vccmii - mii supply. +3.3v or +5v supply for mii. a decoupling capacitor to digital ground should be supplied for these pins. 7, 14, 39, 56, 59, 77, 95, 160 gnd - digital ground . ground return for digital supply. 21 gnda - analog ground . ground return for analog supply. 108 gndh - ground. ground return for core analog circuitry. 107 vcch - supply. +5v supply for core analog circuitry. 128, 137, 147, 156 vcct - transmit power supply. +5v supply for transmit circuits. 127, 136, 146, 155 gndt - transmit ground . ground return for transmit supply. 125, 134, 144, 153, vccr - receive power supply. +5v supply for all receive circuits. 121, 122, 131, 141, 150 gndr - receive ground . ground return for receive supply. table 12: lxt975a power supply signal descriptions pin# symbol type signal description 22, 60, 96 vcc - power supply. +5v supply for all digital circuits. 40, 78 vccmii - mii supply. +3.3v or +5v supply for mii. a decoupling capacitor to digital ground should be supplied for these pins. 7, 14, 39, 56, 59, 77, 95, 160 gnd - digital ground . ground return for digital supply. 21 gnda - analog ground . ground return for analog supply. 108 gndh - ground. ground return for core analog circuitry. 107 vcch - supply. +5v supply for core analog circuitry. 128, 135, 147, 154 vcct - transmit power supply. +5v supply for transmit circuits. 127, 134, 146, 153 gndt - transmit ground . ground return for transmit supply. 125, 132, 144, 151, vccr - receive power supply. +5v supply for all receive circuits. 121, 122, 131, 137, 141, 150, 156 gndr - receive ground . ground return for receive supply. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 14 functional description introduction the lxt974a and lxt975a are four-port fast ethernet 10/100 transceivers that support 10 mbps and 100 mbps networks. they comply with all applicable requirements of ieee 802.3. each port can directly drive either a 100base-tx line (>130 meters) or a 10base-t line (>185 meters). figure 3 shows the lxt974a in a typical switch application. figure 3: lxt974a switch application on power-up, the lxt974a/975a uses auto-negotiation/ parallel detection on each port to automatically determine line operating conditions. if the phy device on the other side of the link supports auto-negotiation, the lxt974a/ 975a will auto-negotiate with it using fast link pulse (flp) bursts. if the phy partner does not support auto- negotiation, the lxt974a/975a will automatically detect the presence of either link pulses (10 mbps phy) or idle symbols (100 mbps phy) and set its operating conditions accordingly. the lxt974a/975a interfaces to four 10/100 media access controllers (mac)s through the mii interfaces. it performs all functions of the physical coding sublayer (pcs) and physical media attachment (pma) sublayer as defined in the ieee 802.3 100base-x specification. this device also performs all functions of the physical media dependent (pmd) sublayer for 100base-tx connections. the mii speeds are automatically set once port operating conditions have been determined. the lxt974a/975a provides half-duplex and full-duplex operation at 100 mbps and 10 mbps. it also offers standard loopback mode for switch applications. the lxt974a/ 975a supports the 802.3 mdio register set. specific bits in the registers are referenced using an x.y notation, where x is the register number (0-6 or 16-20) and y is the bit number (0-15). the lxt975a is pin compatible with the lxt974a except for the network ports. each port on the lxt974a provides a combination twisted-pair or pecl interface for a 10/100base-tx or 100base-fx connection. the lxt975a is optimized for stacked rj45 modular applications as shown in figure 4. ports 1 and 3 support the pecl interface for fiber connections and all four ports support the twisted-pair interface for 10/100base-tx connections. figure 4: lxt975a switch application single rj45 selectable 10 or 100 mbps fiber module backplane memory fiber module fiber module fiber module lxt974a 10/100 quad transceiver switch mac asic lxt974a 10/100 quad transceiver lxt974a 10/100 quad transceiver quad transformer quad transformer stacked rj45 10 or 100 mbps lxt975a 10/100 quad transceiver quad transformer fiber module backplane memory fiber module fiber module fiber module lxt974a 10/100 quad transceiver switch mac asic lxt975a 10/100 quad transceiver lxt975a 10/100 quad transceiver lxt975a 10/100 quad transceiver quad transformer quad transformer quad transformer 15 lxt974a/lxt975a functional description network media / protocol support the lxt974a/975a supports both 10base-t and 100base-tx ethernet over twisted-pair, or 100 mbps ethernet over fiber media (100base-fx). a media independent interface (mii) is used for communication with the media access controller (mac). 10/100 mbps network interface each of the four network interface ports consists of four external pins (two differential signal pairs). the pins are shared between twisted-pair (tp) and fiber. signal assignments (input or output, positive or negative) vary depending on whether the port is configured for tp or fiber media. refer to tables 1 through 6 for specific pin assignments. the lxt974a/975a output drivers generate either 100base-tx, 10base-t, or 100base-fx output. when not transmitting data, the lxt974a/975a generates 802.3-compliant link pulses or idle code. input signals are decoded either as a 100base-tx, 100base-fx, or 10base-t input, depending on the mode selected. auto- negotiation/parallel detection or manual control is used to determine the speed of this interface. twisted-pair interface when operating at 100 mbps, mlt3 symbols are continuously transmitted and received. when not transmitting data, the lxt974a/975a generates idle symbols. during 10 mbps operation, manchester-encoded data is exchanged. when no data is being exchanged, the line is left in an idle state. in 100 mbps mode, the lxt974a/975a is capable of driving a 100base-tx connection over 100 w, category 5, unshielded twisted pair (utp). a 10base-t connection can be supported using 100 w category 3, utp. only a transformer (1:1 on receive side, 2:1 on trans- mit side), load resistors, and bypass capacitors are needed to complete this interface. using level one's patented waveshaping technology, the transmitter pre- distorts the outgoing signal to reduce the need for external filters for emi compliance. a 4k w passive load is always present across the twisted-pair inputs. when enabled, the twisted-pair inputs are actively biased to approximately 2.8v. fiber interface the lxt974a/975a provides a pecl interface that complies with the ansi x3.166 specification. this interface is suitable for driving a fiber-optic coupler. the twisted-pair pin assignments are remapped to support the pecl interface. the lxt974a supports both the twisted-pair and fiber interface on all four ports. the lxt975a, optimized for tp operation with dual-high rj45 connectors, provides dual interfaces on ports 1 and 3. during 100base-fx operation, the fibi pins receive differential pecl signals and the fibo pins produce differential pecl output signals. fiber ports cannot be enabled via auto-negotiation; they must be enabled via the hardware control interface or mdio registers. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 16 mii interface the lxt974a/975a supports four standard miis (one per port). this interface consists of a data interface and a management interface. the mii data interface passes data between the lxt974a/975a and one or more media access controllers (macs). separate signals are provided for transmit and receive. this interface operates at either 10 mbps or 100 mbps. the speed is set automatically, once the operating conditions of the network link have been determined. nine signals are used to pass received data to the mac: rxd<3:0>, rx_clk, rx_dv, rx_er, col and crs. seven signals are used to transmit data from the mac: txd<3:0>, tx_clk, tx_en, and tx_er. mii data interface figure 5 shows the data portion of the mii interface. separate channels are provided for transmitting data from the mac to the lxt974a/975a (txd), and for receiving data (rxd) from the line. each channel has its own clock, data bus, and control signals. the lxt974a/975a supplies both clock sig- nals as well as separate outputs for carrier sense and collision. data transmission across the mii is imple- mented in 4-bit-wide nibbles. tristating the mii the lxt974a/975a asserts rx_dv, rxd, rx_clk and rx_er as soon as it receives a packet from the network. when trste n is high, the associ- ated port output signals are tristated. figure 5: mii data interface transmit clock the lxt974a/975a is the master clock source for data transmission. the lxt974a/975a automatically sets the speed of tx_clk to match port conditions. if the port is operating at 100 mbps, tx_clk will be set to 25 mhz. if the port is operating at 10 mbps, tx_clk will be set to 2.5 mhz. the transmit data and control signals must always be synchronized to tx_clk by the mac. the lxt974a/975a nor- mally samples these signals on the rising edge of tx_clk. however, advanced tx_clk mode is available by setting mii register bit 19.5=1. in this mode, the lxt974a/975a samples the transmit data and control signals on the falling edge of tx_clk. when operating under mdio control, the user can advance the transmit clock relative to txd<3:0> and tx_er. when advance tx_clk mode is selected, the lxt974a/975a clocks txd data in on the falling edge of tx_clk, instead of the rising edge. this mode provides an increase in timing margins of txd, relative to tx_clk. advance tx_clk mode is enabled when bit 19.5 = 1. transmit enable the mac must assert tx_en the same time as the first nibble of preamble, and de-assert tx_en after the last bit of the packet. receive data valid the lxt974a/975a asserts rx_dv when it receives a valid packet. timing changes depend on line operat- ing speed: ? for 100tx and 100fx links, rx_dv is asserted from the first nibble of preamble to the last nibble of the data packet. ? for 10bt links, the entire preamble is truncated. rx_dv is asserted with the first nibble of the start of frame delimiter (sfd) 5d and remains asserted until the end of the packet. error signals whenever the lxt974a/975a receives an errored symbol from the network, it asserts rx_er and drives 1110 on the rxd pins. when the mac asserts tx_er, the lxt974a/975a will drive h symbols out on the line. lxt974a/975a media access controller mac rx_clk n rxd<3:0> n rx_dv n rx_er n tx_clk n txd<3:0> n tx_en n tx_er n crs n col n lxt974a/lxt975a functional description 17 carrier sense carrier sense (crs) is an asynchronous output. it is always generated when a packet is received from the line and in some modes when a packet is transmitted. on transmit, crs is asserted on a 10 mbps or 100 mbps half-duplex link. carrier sense is not generated on transmit when the link is operating in full-duplex mode. usage of crs for interframe gap (ifg) timing is not recommended for the following reasons: ? de-assertion time for crs is slightly longer than assertion time. this causes ifg intervals to appear somewhat shorter to the mac than it actually is on the wire. ? crs de-assertion is not aligned with tx_en de- assertion on transmit loopbacks in half-duplex mode. operational loopback operational loopback is provided for 10 mbps half- duplex links when bit 19.11 = 0. data transmitted by the mac will be looped back on the receive side of the mii. operational loopback is not provided for 100 mbps links, full-duplex links, or when 19.11 = 1. test loopback a test loopback function is provided for diagnostic testing of the lxt974a/lxt975a. during test loop- back, twisted-pair and fiber interfaces are disabled. data transmitted by the mac is internally looped back by the lxt974a/975a and returned to the mac. test loopback is available for 100tx, 100fx, and 10t operation.test loopback is enabled by setting bit 0.14 = 1, bit 0.8 = 1 (full-duplex), and bit 0.12 = 0 (disable auto-negotiation). the desired mode of operation for test loopback is set using bits 0.13 and 19.2 as shown in table 13. loopback paths for the three modes of operation are shown in figure 6. figure 6: loopback paths collision the lxt974a/975a asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. table 14 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. table 13: test loopback operation mode of operation bit 19.2 0.13 10t test loopback 0 0 100tx test loopback 0 1 100fx test loopback 1 1 1. bit 0.14 = 1, bit 0.8 = 1, and 0.12 = 0 must also be set to enable test loopback. digital block mii analog block fx driver tx driver 100tx loopback 100fx loopback 10t loopback table 14: carrier sense, loopback, and collision conditions speed & duplex condition carrier sense loopback collision full-duplex at 10 mbps or 100 mbps receive only none none 100 mbps, half-duplex transmit or receive none transmit and receive 10 mbps, half-duplex, 19.11 = 0 transmit or receive yes transmit and receive 10 mbps, half-duplex, 19.11 = 1 transmit or receive none transmit and receive 18 lxt974a/lxt975a fast ethernet 10/100 quad transceiver mii management interface the lxt974a/975a supports the ieee 802.3 mii management interface also known as the management data input/output (mdio) interface. this interface allows upper-layer devices to monitor and control the state of the lxt974a/975a. the mdio interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. some registers are required and their functions are defined by the ieee 802.3 specifi- cation. additional registers are allowed for expanded functionality. the lxt974a/975a is configured with both sets of registers. the physical interface consists of a data line (mdio) and clock line (mdc). operation of this interface is controlled by the mddis input pin. when mddis is high, the mdio operates as a read-only interface. when mddis is low, both read and write are enabled. the timing for the mdio interface is shown in table 40 on page 53. the protocol is shown in fig- ures 7 and 8 (read and write). the protocol allows one controller to communicate with up to eight lxt974a/975a chips. bits a4:2 of the 5-bit phy address are assigned as the lxt974a/975a address. bits a1:0 are assigned as port addresses 0 through 3. the lxt974a/975a supports 12 internal registers per port (48 total), each of which is 16 bits wide. figure 7: management interface - read frame structure figure 8: management interface - write frame structure mii interrupts the lxt974a/975a provides interrupt signals in two ways. the mdio interrupt reflects the interrupt status of each port addressed by the read. details are shown in figure 9. setting bit 17.1 = 1 on all four ports, enables global interrupts using the mdint pin. an active low on this pin indicates a status change on the lxt974a/975a. interrupts may be caused by: ? link status change ? auto-negotiation complete ? full-duplex status change ? jabber detect figure 9: mdio interrupt signaling mdc mdio (read) 32 "1"s 0110 preamble sfd op code phy address turn around z0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 data idle write read d15 d14 d1 d0 idle mdc mdio (write) 32 "1"s 0101 preamble sfd op code phy address turn around 1 0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 d0 data idle idle write mdc mdio interrupt turn around z idle 0 int read data sourced by phy mdio frame 19 lxt974a/lxt975a functional description hardware control interface the hardware control interface is used to configure operating characteristics of the lxt974a/975a. when mddis is low, this interface provides initial values for the mdio registers, and then passes control to the mdio interface. when mddis is high, this interface provides continuous control over the lxt974a/975a. individual chip addressing allows multiple lxt974a/975a devices to share the mii in either mode. tables 15 through 17 show how to set up the desired operating configurations using the hardware control interface. table 15: configuring the lxt974a/975a via hardware control desired configuration pin name input value mdio registers auto-negotiation enabled on all ports 1, 2, 3 autoena high 0.12 = 1 sd/tp n low 19.2 = 0 auto-negotiation disabled on all ports 4 autoena low 0.12 = 0 scrambler bypassed on all ports bypscr high 19.3 = 1 scrambler enabled on all ports bypscr low 19.3 = 0 1. sd/tp n must be set low for auto-negotiation operation. 2. refer to table 16 for hardware control interface functions advertised when auto-negotiation is enabled. 3. fiber operation can be forced per port via sd/tp n pins when auto-negotiation is enabled. see table 17 for details. 4. refer to table 17 for hardware control interface functions available when auto-negotiation is disabled. table 16: configuring lxt974a/975a auto-negotiation advertisements via hardware control desired configuration 1,2 pin settings mdio registers sd/tp n (per port) fde (global) cfg_2 (global) cfg_1 (global) cfg_0 3 (global) 4.5 4.6 4.7 4.8 advertise all low ignore low low ignore1111 advertise 100 hd low low high low ignore0010 advertise 100 hd/fd low high high low ignore0011 advertise 10 hd low low low high ignore1000 advertise 10 hd/fd low high low high ignore1100 advertise 10/100 hd low low high high ignore1010 1. refer to table 15 for basic configurations. 2. refer to table 17 for hardware control interface functions available when auto-negotiation is disabled. 3. auto-negotiation is not affected by cfg_0. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 20 table 17: configuring the lxt974a/975a with auto-negotiation disabled desired configuration 1,2 pin settings mdio registers sd/tp n per port cfg_2 global cfg_0 global fde global fde_fx 0.8 0.13 19.2 per port (fiber) configuration fiber operation can be forced per port via sd/tp n pins when auto-negotiation is enabled. per-port settings override the global pin settings. 100fx full-duplex operation. high or pecl 3 ignored ignored ignored high 1 1 1 100fx half-duplex operation. high or pecl 3 ignored ignored ignored low 0 1 1 global (twisted-pair) configuration 5 force 100tx full-duplex operation on all ports. 4 low low high high ignored 1 1 0 force 100tx half-duplex operation on all ports. 4 low low high low ignored 0 1 0 force 10t full-duplex operation on all ports. low low low high ignored 1 0 0 force 10t half-duplex operation on all ports. low low low low ignored 0 0 0 1. refer to table 15 for basic configurations. 2. refer to table 16 for hardware control interface functions advertised when auto-negotiation is enabled. 3. when sd/tp n is set high or to pecl levels, auto-negotiation is disabled and fde_fx determines the duplex mode of the port. 4. cfg_2, cfg_0, and sd/tp n must all be set for 100tx operation. 5. fiber configuration must be selected on a per-port basis. lxt974a/lxt975a functional description 21 initialization at power-up or reset, the lxt974a/975a performs the initialization as shown in figure 10. control mode selection is provided via the mddis pin as shown in table 18. when mddis (pin 100) is high, the lxt974a/975a operates in manual control mode. when mddis is low, the lxt974a/975a operates in mdio control mode. mdio control mode in the mdio control mode, the lxt974a/975a uses the hardware control interface to set up initial (default) values of the mdio registers. the mdio register set for the lxt974a/975a is described in tables 44 through 55. specific bits in the registers are referenced using an x.y notation, where x is the register number (0-6 or 16-20) and y is the bit number (0-15). once initial values are set, bit control reverts to the mdio interface. manual control mode in the manual control mode, lxt974a/975a disables direct write operations to the mdio registers via the mdio interface. the hardware control interface is continuously monitored and the mdio registers are updated accord- ingly. link configuration when the lxt974a/975a is first powered on, reset, or encounters a link failure state, it must determine the line speed and operating conditions to use for the network link. the lxt974a/975a first checks the hardware control interface pins and mdio registers. using these mechanisms, the user can command the lxt974a/975a to do one of the following: ? force network link to 100fx (fiber). ? force network link operation to: 100tx, full-duplex 100tx, half-duplex 10base-t, full-duplex 10base-t, half-duplex ? allow auto-negotiation/parallel-detection. the hard- ware control interface pins are used to set the state of the mdio advertisement registers. when forcing the network link, the lxt974a/975a immediately begins operating the network interface as commanded. when auto-negotiation is enabled, the auto- negotiation / parallel-detection operation begins. table 18: mode control settings mode mddis pin 100 reset pin 109 pwr dwn pin 102 mdio control low high low manual control high high low reset - low low power down - - high figure 10: hardware interface mode selection power-up or reset check value mddis hi g h low mdio control mode exit manual control mode disable mdio writes read h/w control interface initialize mdio registers read h/w control interface pass control to mdio interface update mdio registers 22 lxt974a/lxt975a fast ethernet 10/100 quad transceiver auto-negotiation the lxt974a/975a attempts to auto-negotiate with its counterpart across the link by sending fast link pulse (flp) bursts. each burst consists of 33 link pulses spaced 62.5 m s apart. odd link pulses (clock pulses) are always present. even link pulses (data pulses) may be present or absent to indicate a 1 or a 0. each flp burst exchanges 16 bits of data, which are referred to as a page. all devices that support auto-negotiation must support a base page as defined in the ieee 802.3 standard. by exchanging base pages, the lxt974a/975a and its link partner communicate their capabilities to each other. both sides must receive at least three identical base pages for negotiation to proceed. each side finds the highest common capabilities that both sides support. both sides then exchange more pages, and finally agree on the operating state of the line. parallel detection in parallel with auto-negotiation, the lxt974a/975a also monitors for 10 mbps normal link pulses (nlp) or 100 mbps idle symbols. if either is detected, the device automatically reverts to the corresponding operating mode. parallel detection allows the lxt974a/975a to communicate with devices that do not support auto- negotiation. controlling auto-negotiation when auto-negotiation is controlled by software, the following steps are recommended: ? after power-up, power-down, or reset, the power- down recovery time, as specified in table 41 on page 54, must be exhausted before proceeding. ? set the auto-negotiation advertisement register bits. ? enable auto-negotiation by setting mdio bit 0.12 = 1. monitoring auto-negotiation when auto-negotiation is being monitored, the following apply: ? bit 20.13 is set to 1 once the link is established. ? bits 20.12 and 20.11 can be used to determine the link operating conditions (speed and duplex). figure 11: lxt974a/975a auto-negotiation operation check value 0.12 start done enable auto-neg/parallel detection go to forced settings attempt auto- negotiation listen for 10t link pulses listen for 100tx idle symbols link set no yes power-up, reset, link failure disable auto-negotiation 0.12 = 0 0.12 = 1 lxt974a/lxt975a functional description 23 100 mbps operation 100base-x mii operations the lxt974a/975a encodes and scrambles the data sent by the mac, and then transmits it using mlt3 signaling. the lxt974a/975a descrambles and decodes mlt3 data received from the network. when the mac is not actively transmitting data, the lxt974a/975a sends out idle symbols. the 100base-x protocol specifies the use of a 5-bit symbol code on the network media. however, data is normally transmitted across the mii interface in 4-bit nibbles. the lxt974a/975a incorporates a 4b/5b encoder/decoder circuit that translates 4-bit nibbles from the mii into 5-bit symbols for the 100base-x connection, and translates 5-bit symbols from the 100base-x connection into 4-bit nibbles for the mii. figure 12 shows the data conversion flow from nibbles to symbols. table 19 on page 24 shows 4b/5b symbol coding (not all symbols are valid). 100base-x network operations during 100base-x operation, the lxt974a/975a transmits and receives 5-bit symbols across the network link. figure 13 shows the structure of a standard frame packet. when the mac is not actively transmitting data, the lxt974a/975a sends out idle symbols on the line. in 100tx mode, the lxt974a/975a scrambles the data and transmits it to the network using mlt-3 line code. the mlt-3 signals received from the network are descrambled and decoded and sent across the mii to the mac. in 100fx mode, the lxt974a/975a transmits and receives nrzi signals across the pecl interface. an external 100fx transceiver module is required to complete the fiber connection. as shown in figure 13, the mac starts each transmission with a preamble pattern. as soon as the lxt974a/975a detects the start of preamble, it transmits a j/k symbol (start of stream delimiter, ssd) to the network. it then encodes and transmits the rest of the packet, including the balance of the preamble, the start of frame delimiter (sfd), packet data, and crc. once the packet ends, the lxt974a/975a transmits the t/r symbol end of stream delimiter (esd) and then returns to transmitting idle symbols. figure 12: 100base-tx data flow figure 13: 100base-tx frame structure d0 d1 d2 d3 parallel to serial serial to parallel d0 d1 d2 d3 4b/5b 5b/4b s0 s1 s2 s3 s4 mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scramble de- scramble standard mii mode data flow 1. four independent mii ports serve four independent network ports. network port configurations are independently selectable. m ii port speed is set to match the associated network port. 2. the scrambler can be bypassed by setting 19.3 = 1. p0 p1 p6 sfd 64-bit preamble (8 octets) start of frame delimiter (sfd) da da sa sa destination and source address (6 octets each) l1 l2 packet len g th (2 octets) d0 d1 dn data field (pad to minimum packet size) frame check field (4 octets) crc i0 interframe gap / idle code (> 12 octets) replaced by /t/r/ code- g roups end of stream delimiter (esd) ifg replaced by /j/k/ code- g roups start of stream delimiter (ssd) lxt974a/lxt975a fast ethernet 10/100 quad transceiver 24 table 19: 4b/5b coding code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 1 0 6 0 1 1 1 0 data 6 data 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f idle undefined i 1 1 1 1 11 idle. used as inter-stream fill code 0 1 0 1 j 2 1 1 0 0 0 start of stream delimiter (ssd), part 1 of 2 control 0 1 0 1 k 2 1 0 0 0 1 start of stream delimiter (ssd), part 2 of 2 undefined t 3 0 1 1 0 1 end of stream delimiter (esd), part 1 of 2 undefined r 3 0 0 1 1 1 end of stream delimiter (esd), part 2 of 2 undefined h 4 0 0 1 0 0 transmit error. used to force signaling errors undefined invalid 0 0 0 0 0 invalid undefined invalid 0 0 0 0 1 invalid undefined invalid 0 0 0 1 0 invalid invalid undefined invalid 0 0 0 1 1 invalid undefined invalid 0 0 1 0 1 invalid undefined invalid 0 0 1 1 0 invalid undefined invalid 0 1 0 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 1 0 0 0 0 invalid undefined invalid 1 1 0 0 1 invalid 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition. lxt974a/lxt975a functional description 25 100base-x protocol sublayer operations with respect to the 7-layer communications model, the lxt974a/975a is a physical layer 1 (phy) device. the lxt974a/975a implements the physical coding sublayer (pcs), physical medium attachment (pma), and physical medium dependent (pmd) sublayers of the reference model defined by the ieee 802.3u specification. the following paragraphs discuss lxt974a/975a operation from the reference model point of view. pcs sublayer the physical coding sublayer (pcs) provides the mii interface, as well as the 4b/5b encoding/decoding function. for 100tx and 100fx operation, the pcs layer provides idle symbols to the pmd-layer line driver as long as tx_en is de-asserted. for 10t operation, the pcs layer merely provides a bus interface and serialization/de-serialization function. 10t operation does not use the 4b/5b encoder. preamble handling when the mac asserts tx_en, the pcs substitutes a /j/k symbol pair, also known as the start of stream delimiter (ssd), for the first two nibbles received across the mii. the pcs layer continues to encode the remaining mii data, following table 19 on page 24, until tx_en is de-asserted. it then returns to supply- ing idle symbols to the line driver. in the receive direction, the pcs layer performs the opposite function, substituting two preamble nibbles for the ssd. figure 14: lxt974a/975a protocol sublayers encoder/decoder serializer/de-serializer link/carrier detect pcs sublayer pma sublayer mii interface pecl interface fiber transceiver lxt974a 100base-tx 100base-fx scrambler/ de-scrambler pmd sublayer 26 lxt974a/lxt975a fast ethernet 10/100 quad transceiver data errors figure 15 shows normal reception. when the lxt974a/975a receives invalid symbols from the line, it asserts rx_er, as shown in figure 16. collision indication figure 17 shows normal transmission. the lxt974a/ 975a detects a collision if transmit and receive are active at the same time. as shown in figure 18, upon detection of a collision, the col output is asserted and remains asserted for the duration of the collision. figure 15: 100base-tx reception with no errors figure 16: 100base-tx reception with invalid symbol figure 17: 100base-tx transmission with no errors figure 18: 100base-tx transmission with collision rx_clk rx_dv rxd<3:0> rx_er sfd sfd da da da da crc crc crc crc preamble rx_clk rx_dv rxd<3:0> rx_er sfd sfd da da da xx xx xx xx xx xx xx xx xx preamble tx_clk tx_en txd<3:0> crs col prea mbl e da da da da da da da da da tx_clk tx_en txd<3:0> crs col prea mbl e jam jam jam jam 27 lxt974a/lxt975a functional description pma sublayer link the lxt974a/975a supports a standard link algo- rithm or enhanced link algorithm, which can be set via bit 16.1. link is established when the symbol error rate is less than 64 errors out of 1024 symbols received. once the link is established: when standard link algorithm is selected (default, bit 16.1 = 0), the link will go down when the symbol error rate becomes greater than 64 out of 1024. when enhanced link algorithm is selected (bit 16.1 = 1), the link will go down if twelve idle symbols in a row are not received within 1 to 2 ms. this mode makes it more difficult to bring the link down. in either mode, the lxt974a/975a reports link fail- ure via the mii status bits (1.2, 18.15, and 20.13) and interrupt functions. if auto-negotiate is enabled, link failure causes the lxt974a/975a to re-negotiate. link failure override the lxt974a/975a will normally transmit 100 mbps data packets or idle symbols only if it detects the link is up, and transmits only flp bursts if the link is not up. setting bit 19.14 = 1 overrides this function, allowing the lxt974a/975a to transmit data packets even when the link is down. this feature is provided as a diagnostic tool. note that auto-negotiation must be disabled to transmit data packets in the absence of link. if auto-negotiation is enabled, the lxt974a/975a will automatically begin transmitting flp bursts if the link goes down. carrier sense (crs) for 100tx and 100fx links, a start of stream delimiter or /j/k symbol pair causes assertion of carrier sense (crs). an end of stream delimiter, or /t/r symbol pair causes de-assertion of crs. the pma layer will also de-assert crs if idle symbols are received without /t/r; however, in this case rx_er will be asserted for one clock cycle when crs is de-asserted. for 10t links, crs assertion is based on reception of valid preamble, and de-assertion on reception of an end of frame (eof) marker. twisted-pair pmd sublayer the twisted-pair physical medium dependent (pmd) layer provides the signal scrambling and descrambling, line coding and decoding (mlt-3 for 100tx, manchester for 10t), as well as receiving, polarity correction, and baseline wander correction functions. scrambler/descrambler (100tx only) the purpose of the scrambler is to spread the signal power spectrum and further reduce emi using an 11-bit, non-data-dependent polynomial. the receiver automatically decodes the polynomial whenever idle symbols are received. the scrambler/descrambler can be bypassed by either setting bit 19.3 = 1 or setting pin (bypscr) high. the scrambler is automatically bypassed when the fiber port is enabled. scramber bypass is provided for diagnostic and test support. baseline wander correction the lxt974a/975a provides a baseline wander cor- rection function which makes the device robust under all network operating conditions. the mlt3 coding scheme used in 100base-tx is by definition unbal- anced. this means that the dc average value of the signal voltage can wander significantly over short time intervals (tenths of seconds). this wander can cause receiver errors, particularly in less robust designs, at long line lengths (100 meters). the exact characteristics of the wander are completely data dependent. the lxt974a/975a baseline wander correction char- acteristics allow the lxt974a/975a to recover error- free data while receiving worst-case killer packets over a variety of cable distances. polarity correction the lxt974a/975a automatically detects and cor- rects for the condition where the receive signal (tpip/ n) is inverted. reversed polarity is detected if eight inverted link pulses, or four inverted end of frame (eof) markers, are received consecutively. if link pulses or data are not received by the maximum receive time-out period, the polarity state is reset to a non-inverted state. fiber pmd sublayer the lxt974a/975a provides a pecl interface for connection to an external fiber-optic transceiver. (the external transceiver provides the pmd function for fiber media.) the lxt974a/975a uses an nrzi format for the fiber interface. the fiber interface operates at 100 mbps and does not support 10fl applications. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 28 10 mbps operation the lxt974a/975a will operate as a standard 10base-t transceiver. data transmitted by the mac as 4-bit nibbles is serialized, manchester-encoded, and transmitted on the tpop/n outputs. received data is decoded and de-serial- ized into 4-bit nibbles. the lxt974a/975a supports all the standard 10 mbps functions. 10base-t mii operation the mac transmits data to the lxt974a/975a via the mii interface. the lxt974a/975a converts the digital data from the mac into an analog waveform that is transmitted to the network via the copper interface. the lxt974a/975a converts analog signals received from the network into a digital format suitable for the mac. the lxt974a/975a sends the received data to the mac via the mii. 10base-t network operations during 10base-t operation, the lxt974a/975a transmits and receives manchester-encoded data across the network link. when the mac is not actively transmitting data, the lxt974a/975a sends out link pulses on the line. in 10base-t mode, the polynomial scrambler/ descrambler is inactive. manchester-encoded signals received from the network are decoded by the lxt974a/ 975a and sent across the mii to the mac. the lxt974a/975a does not support fiber connections at 10 mbps. preamble handling in 10base-t mode, the lxt974a/975a strips the entire preamble off of received packets. crs is asserted a few bit times after carrier is detected. rx_dv is held low for the duration of the preamble. when rx_dv is asserted, the very first two nibbles driven by the lxt974a/975a are the sfd 5d hex followed by the body of the packet. in 10t loopback, the lxt974a/975a loops back whatever the mac transmits to it, including the preamble. link test in 10 mbps mode, the lxt974a/975a always transmit link pulses. if the link test function is enabled, it monitors the connection for link pulses. once link pulses are detected, data transmission will be enabled and will remain enabled as long as either the link pulses or data transmission continue. if the link pulses stop, the data transmission will be disabled. if the link test function is disabled, the lxt974a/ 975a will transmit to the connection regardless of detected link pulses. the link test function can be dis- abled by setting bit 19.8 = 1 or by setting autoena to disable auto-negotiation and setting cfg_1 input high. link failure link failure occurs if link test is enabled and link pulses or packets stop being received. if this condition occurs, the lxt974a/975a returns to the auto- negotiation phase if auto-negotiation is enabled. sqe (heartbeat) by default, the sqe (heartbeat) function is disabled on the lxt974a/975a. to enable this function, set bit 19.10 =1. when this function is enabled, the lxt974a/975a will assert its col output after each transmit packet. see figure 31 on page 51 for sqe timing parameters. jabber if mac transmission exceeds the jabber timer, the lxt974a/975a will disable the transmit and loop- back functions and enable the col pin. see figure 32 on page 51 for jabber timing parameters. the lxt974a/975a automatically exits jabber mode after the unjab time has expired. this function can be disabled by setting bit 19.9 = 1. 29 lxt974a/lxt975a functional description led functions the lxt974a/975a provides three programmable leds per port. refer to table 51 on page 62 for led program- ming details. the lxt974a/975a also provides a serial led output. serial led output the lxt974a/975a provides a serial led interface which should be attached to an external shift register. this interface provides 24 status bits (6 x 4 ports). each port reports the following conditions: ? transmit (t) 0 = transmit active 1 = transmit inactive ? receive (r) 0 = receive active 1 = receive inactive ?link (l) 0 = link active 1 = link inactive ?duplex (d) 0 = half-duplex 1 = full-duplex ? speed (s) 0 = 100 mbps 1 = 10 mbps ? collision (c) 0 = collision active 1 = collision inactive led data is output on leddat in sets of 24 bits. the serial burst is repeated every 1 ms. a status change in any bit also triggers an immediate serial burst (following the minimum inter-burst gap of 10 m s). ledena is driven high for the duration of the leddat output. per port leds the lxt974a/975a provides three led outputs for each port (led n _0, led n _1 and led n _2, where n = port number). these outputs can directly drive leds to indicate activity and collision status. the active low on times are normally extended for improved led visibility. the on- time extension can be disabled by setting bit 16.0 = 1. led n _0 in default mode, led_0 indicates transmitter active. however, led n _0 is programmable and may also be set to indicate receiver active, link, or full-duplex status. refer to led configuration register, table 51 on page 62, for details on programming options. led n _1 in default mode, led_1 indicates receiver active. however, led n _1 is programmable and may also be set to indicate link status, full-duplex status or operating speed. refer to led configuration register, table 51 on page 62, for details on programming options. led n _2 in default mode, active low output indicates link up. however, led n _2 is programmable and may also be set to indicate full-duplex status, operating speed or collision. refer to led configuration register, table 51 on page 62, for details on programming options. table 20: led-dat serial port bit assignments port 0 port 1 port 2 port 3 23 1 22 21 20 19 18 17 16 15 14 13 12 11 : 6 5 4 3 2 1 0 t rldsctrldsc t r l d s c trldsc 1. bit 23 is shifted out first. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 30 operating requirements power requirements the lxt974a/975a requires four +5v supply inputs (vcc, vccr, vcct, and vcch). these inputs may be supplied from a single source although decoupling is required to each respective ground. as a matter of good practice, these supplies should be as clean as possible. typical filtering and decoupling are shown in figure 21 on page 37. mii power requirements an additional supply may be used for the mii (vcc- mii). the supply may be either +5v or +3.3v. when the mii supply is 3.3v, mii inputs may not be driven with 5v levels. vccmii should be supplied from the same power source used to supply the controller on the other side of the mii interface. refer to table 25 on page 42 for mii i/o characteristics. low-voltage fault detect the lxt974a/975a has a low-voltage fault detection function that prevents transmission of invalid symbols when vcc goes below normal operating levels. this function disables the transmit outputs when a low- voltage fault on vcc occurs. if this condition happens, bit 20.2 is set high. operation is automatically restored when vcc returns to normal. table 27 on page 43 indicates voltage levels used to detect and clear the low-voltage fault condition. power down mode the lxt974a/975a goes into power down mode when pwrdwn is asserted. in this mode, all func- tions are disabled except the mdio. the power sup- ply current is significantly reduced. this mode can be used for energy-efficient applications or for redundant applications where there are two devices and one is left as a standby. when the lxt974a/975a is returned to normal operation, configuration settings of the mdio registers are maintained. refer to table 23 on page 41 for power down specifications. clock requirements the lxt974a/975a requires a constant 25 mhz clock (clk25m) that must be enabled at all times. refer to test specifications, table 26 on page 42, for clock timing requirements. 31 lxt974a/lxt975a application information application information design recommendations the lxt974a/975a is designed to comply with ieee requirements and to provide outstanding receive bit error rate (ber) and long-line-length performance. lab testing has shown that the lxt974a/975a can perform well beyond the required distance of 100 meters. to achieve maximum performance from the lxt974a/975a, attention to detail and good design practices are required. refer to the lxt974a/975a design and layout guide for detailed design and layout information. general design guidelines adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. up to 50 mv of noise is considered acceptable. 50 to 80 mv of noise is considered marginal. high-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: ? fill in unused areas of the signal planes with solid copper and attach them with vias to a vcc or ground plane that is not located adjacent to the signal layer. ? use ample bulk and decoupling capacitors throughout the design (a value of .01 m f is recommended for decoupling caps). ? provide ample power and ground planes. ? provide termination on all high-speed switching signals and clock lines. ? provide impedance matching on long traces to prevent reflections. ? route high-speed signals next to a continuous, unbroken ground plane. ? filter and shield dc-dc converters, oscillators, etc. ? do not route any digital signals between the lxt974a/975a and the rj45 connectors at the edge of the board. ? do not extend any circuit power and ground plane past the center of the magnetics or to the edge of the board. use this area for chassis ground, or leave it void. power supply filtering power supply ripple and digital switching noise on the vcc plane can cause emi problems and degrade line performance. it is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having these problems: ? poorly-regulated or over-burdened power supplies. ? wide data busses (>32-bits) running at a high clock rate. ? dc-to-dc converters. many of these issues can be improved just by following good general design guidelines. in addition, level one also recommends filtering between the power supply and the analog vcc pins of the lxt974a/975a. filtering has two benefits. first, it keeps digital switching noise out of the analog circuitry inside the lxt974a/975a, which helps line performance. second, if the vcc planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing emi problems. the recommended implementation is to divide the vcc plane into two sections. the digital section supplies power to the digital vcc pin, mii vcc pin, and to the external components. the analog section supplies power to vcch, vcct, and vccr pins of the lxt974a/975a. the break between the two planes should run under the device. in designs with more than one lxt974a/975a, a single continuous analog vcc plane can be used to supply them all. the digital and analog vcc planes should be joined at one or more points by ferrite beads. the beads should produce at least a 100 w impedance at 100 mhz. the beads should be placed so that current flow is evenly distributed. the maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. each lxt974a/975a draws a maximum of 500 ma from the analog supply so beads rated at 750 ma should be used. a bulk cap (2.2 -10 m f) should be placed on each side of each ferrite bead to stop switching noise from traveling through the ferrite. in addition, a high-frequency bypass cap (.01 m f) should be placed near each analog vcc pin. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 32 ground noise the best approach to minimize ground noise is strict use of good general design guidelines and by filtering the vcc plane. power and ground plane layout considerations great care needs to be taken when laying out the power and ground planes. the following guidelines are recom- mended: ? follow the guidelines in the lxt974a/975a layout guide for locating the split between the digital and analog vcc planes. ? keep the digital vcc plane away from the tpop/n and tpip/n signals, away from the magnetics, and away from the rj45 connectors. ? place the layers so that the tpop/n and tpip/n sig- nals can be routed near or next to the ground plane. for emi reasons, it is more important to shield tpop/ n and tpip/n. chassis ground for esd reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. chassis ground should extend from the rj45 connectors to the magnetics, and can be used to terminate unused signal pairs (bob smith termination). in single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kv isolation capacitor. in multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kv isolation to the bob smith termination. mii terminations series termination resistors are not required on the mii signals driven by the lxt974a/975a. the rbias pin the lxt974a/975a requires a 22 k w, 1% resistor directly connected between the rbias pin and ground. place the rbias resistor as close to the rbias pin as possible. run an etch directly from the pin to the resistor, and sink the other side of the resistor to a filtered ground. surround the rbias trace with a filtered ground; do not run high-speed signals next to rbias. 33 lxt974a/lxt975a application information the twisted-pair interface because the lxt974a/975a transmitter uses 2:1 magnet- ics, system designers must take extra precautions to mini- mize parasitic shunt capacitance in order to meet return loss specifications. these steps include: ? use compensating inductor in the output stage (see figure 22 on page 38). ? place the magnetics as close as possible to the lxt974a/975a. ? keep transmit pair traces short. ? route the transmit pair adjacent to a ground plane. the optimum arrangement is to place the transmit traces two to three layers from the ground plane, with no intervening signals. ? some magnetic vendors are producing magnetics with improved return loss performance. use of these improved magnetics increases the return loss budget available to the system designer. ? improve emi performance by filtering the output cen- tertap. a single ferrite bead may be used to supply centertap current to all 4 ports. all four ports draw a combined total of 3 270 ma so the bead should be rated at 3 400 ma. in addition, follow all the standard guidelines for a twisted- pair interface: ? route the signal pairs differentially, close together. allow nothing to come between them. ? keep distances as short as possible; both traces should have the same length. ? avoid vias and layer changes as much as possible. ? keep the transmit and receive pairs apart to avoid cross-talk. ? put all the components for the transmit network on the front side of the board (same side as the lxt974a/ 975a). ? put entire receive termination network on the back side of the board. ? bypass common-mode noise to ground on the in- board side of the magnetics using 0.01 m f capacitors. ? keep termination circuits close together and on the same side of the board. ? always put termination circuits close to the source end of any circuit. the fiber interface the fiber interface consists of a pecl transmit and receive pair to an external fiber-optic transceiver. the transmit pair should be ac-coupled to the transceiver, and biased to 3.7v with a 50 w equivalent impedance. the receive pair can be dc-coupled, and should be biased to 3.0v with a 50 w equivalent impedance. figure 23 on page 39 shows the correct bias networks to achieve these requirements. 34 lxt974a/lxt975a fast ethernet 10/100 quad transceiver magnetics information the lxt974a/975a requires a 1:1 ratio for the receive transformers and a 2:1 ratio for the transmit transformers as shown in table 21. the transformer isolation voltage should be rated at 2 kv to protect the circuitry from static voltages across the connectors and cables. refer to the magnetic manufacturers cross reference guide (application note 73) for a list of suitable magnetic manufacturers and part numbers. the latest version is located on the level one web site (www.level1.com). suitable magnetic part numbers are provided as a reference only. before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for a specific application. magnetics with improved return loss performance level one is working with magnetic vendors to develop magnetic modules with improved return loss characteristics. these improved magnetics simplify the design requirements for meeting ansi x3.263 return loss specifications. table 21: magnetics requirements parameter min nom max units test condition rx turns ratio C 1 : 1 C C tx turns ratio C 2 : 1 C C insertion loss 0.0 C 1.1 db 80 mhz primary inductance 350 C C m h transformer isolation C 2 C kv differential to common mode rejection 40 C C db .1 to 60 mhz 35 C C db 60 to 100 mhz return loss - standard C C -16 db 30 mhz C C -10 db 80 mhz return loss - improved C C -20 db 30 mhz C C -15 db 80 mhz 35 lxt974a/lxt975a application information twisted-pair/ rj45 interface figure 19 shows layout of the lxt974a twisted-pair interface in a single-high rj45 modular application. figure 20 shows layout of the lxt975a twisted-pair interface in a dual-high (stacked) rj45 application. figure 19: typical lxt974a twisted-pair single rj45 modular application rj45 footprint 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 tp1 tpon1 vcct gndt tpop1 vccr tpin1 tpip1 gndr rbias tp2 tpon2 vcct gndt tpop2 vccr tpin2 tpip2 gndr tp3 tpon3 vcct gndt tpop3 vccr tpin3 tpip3 gndr gndr lxt974a 1 40 2 39 3 38 5 36 6 35 8 33 34 4 7 9 10 31 11 30 12 29 13 28 15 26 16 25 18 23 24 14 17 19 20 21 edge of pcb rx tx tx rx rx tx tx rx termination resistors and common mode bypass capacitors are not shown. see "layout requirements" section for recommended application circuit. port 0 port 1 port 2 port 3 amphenol 557571-1 1x4 port single modular jack gnd test tp0 tpon0 vcct gndt tpop0 vccr tpin0 tpip0 gndr single rj45 24682468 13571357 24682468 13571357 18 18 18 18 port 2 port 3 port 1 port 0 lxt974a/lxt975a fast ethernet 10/100 quad transceiver 36 figure 20: typical lxt975a twisted-pair stacked rj45 modular application stacked rj-45s rj45 footprint 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 gnd test tpip0 tpin0 gndr tpop0 vcct gndt tpon0 vccr gndr tp1 tpon1 vcct gndt tpop1 vccr tpin1 tpip1 gndr rbias tpip2 tpin2 gndr tpop2 vcct gndt tpon2 vccr gndr tp3 tpon3 vcct gndt tpop3 vccr tpin3 tpip3 gndr gndr lxt975a 1 40 2 39 3 38 5 36 6 35 8 33 37 34 4 7 9 32 10 31 11 30 12 29 13 28 15 26 16 25 18 23 27 24 14 17 19 22 20 21 24682468 13571357 86428642 75317531 81 18 81 18 edge of pcb rx tx tx rx rx tx tx rx port 0 port 1 port 2 port 3 termination resistors and common mode bypass capacitors are not shown. see "layout requirements" section for recommended application circuit. port 0 port 1 port 2 port 3 port 0 port 3 port 1 port 2 amphenol 2x2 port stacked modular jack 37 lxt974a/lxt975a application information figure 21: lxt974a/975a power and ground connections rbias vcct gndt gnda vccr gndr .01 m f 22k w 1% gnd vcc .01 m f + ferrite bead 10 m f lxt974a/975a vcch gndh 10 m f digital supply plane analog supply plane vccmii +5v 3.3v or +5v .01 m f .01 m f .01 m f lxt974a/lxt975a fast ethernet 10/100 quad transceiver 38 figure 22: typical twisted-pair interface and supply filtering 1. receiver common mode bypass cap may improve ber performance in systems with noisy power supplies. 2. a single ferrite bead (rated at 400 ma) may be used to supply center tap current to all 4 ports. tpip tpin rj45 tpop tpon 75 w vcct gndt 75 w 0.1 m f 0.001 m f/2kv .01 m f 1 50 w 1% 50 w 1% 0.1 m f gndr to twisted-pair network 3 6 1 2 1:1 2:1 lxt974a/975a output stage with compensating inductor 200 w 1% 200 w 1% 320 nh 50 w 50 w 50 w 50 w 50 w 50 w 4 5 8 7 2 39 lxt974a/lxt975a application information figure 23: typical fiber interface fibon n 191 w fibop n fibin n fibip n 191 w 69 w 69 w fiber txcvr to fiber network 0.1 p f 130 w 130 w 80 w 80 w +5 v 0.1 p f td td rd rd 0.01 m f 0.01 m f gnda gnda vccr vcct +5 v 1 sd/tp n lxt974a/975a 1. refer to fiber transceiver manufacturers recommendations for termination circuitry. suitable fiber transceivers include the hfbr-5103 and hfbr-5105. sd 80 w 130 w gnda +5 v lxt974a/lxt975a fast ethernet 10/100 quad transceiver 40 figure 24: typical mii interface lxt974a/ 975a tx_en n gnd txd n <3:0> tx_clk n tx_er n col n rx_dv n rx_er n rx_clk n rxd n <3:0> crs n mdio mdint mdc mii data i/f +5 v vcc vccmii +3.3v or +5v test trste n mddis mii control i/f 0.1 p f 10 m f + 0.1 p f h/w control i/f fde cfg0 cfg2 cfg1 bypscr fde_fx autoena led n _0 led n _1 led n _2 ledena ledclk 330 : 330 : 330 : leddat serial led interface +5 v port leds (4 ports) twisted-pair interface 41 lxt974a/lxt975a test specifications test specifications note tables 22 through 42 and figures 25 through 38 represent the target specifications of the lxt974a/975a. table 22: absolute maximum ratings parameter sym min max units supply voltage v cc -0.3 6 v operating temperature ambient t opa -15 +85 oc case t opc C+120 oc storage temperature t st -65 +150 oc caution exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 23: operating conditions parameter sym min typ 1 max units recommended supply voltage 2 except mii supply v cc 4.75 5.0 5.25 v mii supply v cc mii 3.125 C 5.25 v recommended operating temperature ambient t opa 0C70oc case t opc 0C110oc v cc current 100base-tx i cc CC570ma 100base-fx i cc CC500ma 10base-t i cc CC570ma power down mode i cc C0.53.0ma auto-negotiation i cc CC570ma 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. voltages with respect to ground unless otherwise specified. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 42 table 24: digital i/o characteristics 1 (over recommended range) parameter symbol min typ 2 max units test conditions input low voltage 3 v il CC0.8v C input high voltage 3 v ih 2.0 C C v C input current i i -100 C 100 m a0.0 < v i < v cc output low voltage v ol CC0.4vi ol = 4 ma output high voltage v oh 2.4 C C v i oh = -4 ma 1. applies to all pins except mii pins. refer to table 25 for mii i/o characteristics. 2. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 3. does not apply to clk25m. refer to table 26 for clock input levels. table 25: digital i/o characteristics - mii pins (over recommended range) parameter symbol min typ max units test conditions input low voltage v il CC.8 v C input high voltage v ih 2.0 C C v C input current i i -100 C 100 m a0.0 < v i < v cc output low voltage v ol CC0.4vi ol = 4 ma output high voltage v oh 2.2 C C v i oh = -4 ma, v cc = 3.3v v oh 2.4 C C v i oh = -4 ma, v cc = 5.0v driver output resistance (line driver output enabled) r o 1 50 100 200 w v cc = 3.3v r o 1 50 100 200 w v cc = 5.0v 1. parameter is guaranteed by design; not subject to production testing. table 26: required clk25m characteristics parameter sym min typ max units test conditions input low voltage v il CC.8v C input high voltage v ih 2.0 C C v C input clock frequency tolerance 1 d f C C 100 ppm clock frequency is 25 mhz input clock duty cycle 1 t dc 40 C 60 % C 1. parameter is guaranteed by design; not subject to production testing. 43 lxt974a/lxt975a test specifications table 27: low-voltage fault detect characteristics parameter sym min typ 1 max units test conditions detect fault threshold v lt 3.4C4.0v C clear fault threshold v lh 4.1C4.7v C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 28: 100base-tx transceiver characteristics (over recommended range ) parameter sym min typ 1 max units test conditions peak differential output voltage v p 0.95 C 1.05 v note 2 signal amplitude symmetry vss 98 C 102 % note 2 signal rise/fall time t rf 3.0 C 5.0 ns note 2 rise/fall time symmetry t rfs CC0.5ns note 2 jitter (measured differentially) C C 0.7 1.4 ns C duty cycle distortion C C C +/- 0.5 ns offset from 16ns pulse width at 50% of pulse peak overshoot v o CC 5 % C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at the line side of the transformer, line replaced by 100 w (+/-1%) resistor. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 44 table 29: 100base-fx transceiver characteristics (over recommended range ) parameter sym min typ 1 max units test conditions transmitter peak differential output voltage (single ended) v op 0.6 C 1.5 v C signal rise/fall time t rf C C 1.6 ns 10 45 lxt974a/lxt975a test specifications figure 25: mii - 100base-tx receive timing table 31: mii - 100base-tx receive timing parameters ( over recommended range) parameter sym min typ 1 max units rxd, rx_dv, rx_er setup to rx_clk high t1 10 C C ns rxd, rx_dv, rx_er hold from rx_clk high t2 5 C C ns crs asserted to rxd<3:0>, rx_dv t4 C 8 C bt receive start of j to crs asserted t6 0 15 - 19 20 bt receive start of t to crs de-asserted t7 13 23 - 27 28 bt receive start of j to col asserted t8 0 15 - 19 20 bt receive start of t to col de-asserted t9 13 23 - 27 28 bt 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t6 t7 t4 t8 t9 0ns 250ns crs trste rx_dv rxd<3:0> rx_clk col t1 t2 tpip lxt974a/lxt975a fast ethernet 10/100 quad transceiver 46 figure 26: mii - 100base-tx transmit timing table 32: mii - 100base-tx transmit timing parameters (over recommended range) parameter sym min typ 1 max units txd<3:0>, tx_en, tx_er setup to tx_clk high t1 10 C C ns txd<3:0>, tx_en, tx_er hold from tx_clk high t2 0 -1 C ns tx_en sampled to crs asserted t3 C 2 4 bt tx_en sampled to crs de-asserted t4 C 3 16 bt tx_en sampled to tpop out (tx latency) t5 6 9 14 bt 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t1 t2 t5 t3 t4 0ns 250ns txclk tx_en txd<3:0> tpop crs 47 lxt974a/lxt975a test specifications figure 27: mii - 100base-fx receive timing table 33: mii - 100base-fx receive timing parameters ( over recommended range) parameter sym min typ 1 max units rxd, rx_dv, rx_er setup to rx_clk high t1 10 C C ns rxd, rx_dv, rx_er hold from rx_clk high t2 5 C C ns crs asserted to rxd<3:0>, rx_dv asserted t4 C 8 C bt receive start of j to crs asserted t6 0 13 - 17 20 bt receive start of t to crs de-asserted t7 13 21 - 25 26 bt receive start of j to col asserted t8 0 13 - 17 20 bt receive start of t to col de-asserted t9 13 21 - 25 26 bt 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t6 t7 t4 t8 t9 0ns 250ns crs trste 1 rx_dv rxd<3:0> rx_clk col t1 t2 fibip lxt974a/lxt975a fast ethernet 10/100 quad transceiver 48 figure 28: mii - 100base-fx transmit timing table 34: mii - 100base-fx transmit timing parameters (over recommended range) parameter sym min typ 1 max units txd<3:0>, tx_en, tx_er setup to tx_clk high t1 10 C C ns txd<3:0>, tx_en, tx_er hold from tx_clk high t2 0 -1 C ns tx_en sampled to crs asserted t3 C 2 4 bt tx_en sampled to crs de-asserted t4 C 3 16 bt tx_en sampled to fibop out (tx latency) t5 6 11 14 bt 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t1 t2 t5 t3 t4 0ns 250ns txclk tx_en txd<3:0> fibop crs 49 lxt974a/lxt975a test specifications figure 29: mii - 10base-t receive timing table 35: mii - 10base-t receive timing parameters (over recommended range) parameter sym min typ 1 max units rxd, rx_dv, rx_er setup to rx_clk high t1 10 C C ns rxd, rx_dv, rx_er hold from rx_clk high t2 10 C C ns tpi in to rxd out (rx latency) t3 C C 73 2 bt crs asserted to rxd, rx_dv, rx_er asserted t4 0 C 69 2 bt rxd, rx_dv, rx_er de-asserted to crs de-asserted t5 0 2.5 - 5.5 6 bt tpi in to crs asserted t6 0 4 5 bt tpi quiet to crs de-asserted t7 0 18 19 bt tpi in to col asserted t8 0 4 5 bt tpi quiet to col de-asserted t9 0 18 19 bt 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. crs is asserted. rxd/rx_dv are driven at the start of sfd (64 bt). rx_clk rxd, rx_dv, rx_er crs tpi t 3 t 4 t 2 t 6 t 1 t 7 t 5 col t 8 t 9 lxt974a/lxt975a fast ethernet 10/100 quad transceiver 50 figure 30: mii - 10base-t transmit timing table 36: mii - 10base-t transmit timing parameters (over recommended range) parameter sym min typ 1 max units txd, tx_en, tx_er setup to tx_clk high t1 10 C C ns txd, tx_en, tx_er hold from tx_clk high t2 0 -1 C ns tx_en sampled to crs asserted t3 C 2 4 bt tx_en sampled to crs de-asserted t4 C 8-11 C bt tx_en sampled to tpo out (tx latency) t5 C 3 - 5 C bt 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. tx_clk txd, tx_en, tx_er crs tpo t 1 t 3 t 4 t 5 t 2 51 lxt974a/lxt975a test specifications figure 31: 10base-t sqe (heartbeat) timing figure 32: 10base-t jab and unjab timing table 37: 10base-t sqe (heartbeat) timing parameters (over recommended range) parameter sym min typ 1 max units col (sqe) delay after tx_en off t1 0.65 1.0 1.6 m s col (sqe) pulse duration t2 .5 1.0 1.5 m s 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 38: 10base-t jab and unjab timing parameters (over recommended range) parameter sym min typ 1 max units maximum transmit time t1 20 96 - 128 2 150 ms unjab time t2 250 525 750 ms 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. typical transmit time may be either of these values depending on internal 32 ms clock synchronization. tx_clk tx_en t 1 t 2 col txd col t 1 t 2 tx_en lxt974a/lxt975a fast ethernet 10/100 quad transceiver 52 figure 33: auto negotiation and fast link pulse timing figure 34: fast link pulse timing table 39: auto negotiation and fast link pulse timing parameters (over recommended range) parameter sym min typ 1 max units clock/data pulse width t1 C 100 C ns clock pulse to data pulse t2 55.5 62.5 69.5 m s clock pulse to clock pulse t3 111 125 139 m s flp burst width t4 C 2 C ms flp burst to flp burst t5 8 12 24 ms clock/data pulses per burst C 17 C 33 ea 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. tpop t1 t1 t2 t3 clock pulse data pulse clock pulse tpop t4 t5 flp burst flp burst 53 lxt974a/lxt975a test specifications figure 35: mdio timing when sourced by sta figure 36: mdio timing when sourced by phy table 40: mii timing parameters (over recommended range) parameter sym min typ 1 max units test conditions mdio setup before mdc C 10 C C ns when sourced by sta mdio hold after mdc C 10 C C ns when sourced by sta mdc to mdio output delay C 0 27 300 ns when sourced by phy 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 10 ns (min) mdc mdio 10 ns (min) 0 - 300 ns mdc mdio lxt974a/lxt975a fast ethernet 10/100 quad transceiver 54 figure 37: power down timing figure 38: serial led timing table 41: power down timing parameters (over recommended range) parameter sym min typ 1 max units power down recovery time t pdr C50Cms 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 42: serial led timing parameters (over recommended range) parameter symbol min typ 1 max units ledena setup to ledclk falling edge tena1 5 12 C ns ledena hold from ledclk falling edge tena2 15 21 C ns leddat setup to ledclk falling edge tdat1 5 12 C ns leddat hold from ledclk falling edge tdat2 15 21 C ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. tpdr vcc reset mdio,etc vcc = 4.75v tena1 ledena ledclk leddat tena2 tdat1 tdat2 55 lxt974a/lxt975a register definitions register definitions the lxt974a/975a register set includes a total of 48 16-bit registers, 12 registers per port. refer to table 43 for a com- plete register listing. ? seven base registers (0 through 6) are defined in accordance with the reconciliation sublayer and media indepen- dent interface and physical layer link signaling for 10/100 mbps auto-negotiation sections of the ieee 802.3 specification (register 7, next page, is not supported). ? five additional registers (16 through 20) are defined in accordance with the ieee 802.3 specification for adding unique chip functions. table 43: register set address register name bit assignments 0 control register refer to table 44 1 status register refer to table 45 2 phy identification register 1 refer to table 46 3 phy identification register 2 refer to table 47 4 auto-negotiation advertisement register refer to table 48 5 auto-negotiation link partner ability register refer to table 49 6 auto-negotiation expansion register refer to table 50 16 led configuration register refer to table 51 17 interrupt enable register refer to table 52 18 interrupt status register refer to table 53 19 port configuration register refer to table 54 20 port status register refer to table 55 lxt974a/lxt975a fast ethernet 10/100 quad transceiver 56 table 44: control register bit name description type 1 default 0.15 reset 1 = reset port. 0 = enable normal operation. r/w sc 0 0.14 loopback 1 = enable loopback mode. 0 = disable loopback mode. r/w 0 0.13 speed selection 1 = 100 mbps. 0 = 10 mbps. r/w note 2 0.12 auto-negotiation enable 1 = enable auto-negotiate process (overrides speed select and duplex mode bits). 0 = disable auto-negotiate process. r/w note 3 0.11 power down 1 = enable power down. 0 = enable normal operation. r/w note 4 0.10 isolate 1 = electrically isolate port from mii. 0 = normal operation. r/w note 5 0.9 restart auto- negotiation 1 = restart auto-negotiation process. 0 = normal operation. r/w sc note 6 0.8 duplex mode 1 = enable full-duplex. 0 = enable half-duplex. r/w note 7 0.7 collision test 1 = enable col signal test. 0 = disable col signal test. r/w note 8 0.6:4 transceiver test mode not supported. ro 0 0.3 master-slave enable not supported. ro 0 0.2 master-slave va l u e not supported. ro 0 0.1:0 reserved write as 0; ignore on read. r/w n/a 1. r/w = read/write ro = read only sc = self clearing 2. if auto-negotiation is enabled, this bit is ignored. if auto-negotiation is disabled, the default value of bit 0.13 is deter mined by cfg_0. 3. if sd_tx n is tied high or to a 5v pecl input (fx mode), the default value of bit 0.12 = 0. if sd_tx n is tied low (tp mode), the default value of bit 0.12 is determined by autoena. 4. the lxt974a/975a will internally hold all set values of the configuration registers upon exiting power down mode. a delay of 500 ns minimum is required from the time power down is cleared until any register can be written. 5. the default value of bit 0.10 is determined by pin trste n . 6. if auto-negotiation is enabled, the default value of bit 0.9 is determined by cfg_0. if auto-negotiation is disabled, the bit is ignored. 7. if auto-negotiation is enabled, this bit is ignored. if auto-negotiation is disabled and the port is operating in tx mode, t he default value of bit 0.8 is determined by pin fde. if auto-negotiation is disabled and the port is operating in fx mode, the default value of bit 0.8 i s determined by pin fde_fx. 8. this bit is ignored unless loopback is enabled (bit 0.14 = 1). 57 lxt974a/lxt975a register definitions table 45: status register (address 1) bit name description type 1 default 1.15 100base-t4 not supported. ro 0 1.14 100base-x full-duplex 1 = port able to perform full-duplex 100base-x. ro 1 1.13 100base-x half-duplex 1 = port able to perform half-duplex 100base-x. ro 1 1.12 10 mbps full- duplex 1 = port able to operate at 10 mbps in full-duplex mode. ro 1 1.11 10 mbps half-duplex 1 = port able to operate at 10 mbps in half-duplex mode. ro 1 1.10 100base-t2 full-duplex not supported. ro 0 1.9 100base-t2 half-duplex not supported. ro 0 1.8 reserved ignore on read. ro 0 1.7 master-slave configuration fault not supported. ro 0 1.6 mf preamble suppression 0 = port will not accept management frames with preamble suppressed. ro 0 1.5 auto-negotiation complete 1 = auto-negotiation process complete. 0 = auto-negotiation process not complete. ro 0 1.4 remote fault 1 = remote fault condition detected. 0 = no remote fault condition detected. ro/lh 0 1.3 auto-negotiation ability 1 = port is able to perform auto-negotiation. ro 1 1.2 link status 1 = link is up. 0 = link is down. ro/ll 0 1.1 jabber detect (10base-t only) 1 = jabber condition detected. 0 = no jabber condition detected. ro/lh 0 1.0 extended capability 1 = extended register capabilities. ro 1 1. ro = read only ll = latching low lh = latching high lxt974a/lxt975a fast ethernet 10/100 quad transceiver 58 figure 39: phy identifier bit mapping table 46: phy identification register 1 (address 2) bit name description type 1 default 2.15:0 phy id number the phy identifier composed of bits 3 through 18 of the oui. ro 7810 hex 1. ro = read only table 47: phy identification register 2 (address 3) bit name description type 1 default 3.15:10 phy id number the phy identifier composed of bits 19 through 24 of the oui. ro 000000 3.9:4 manufacturers model number 6 b i t s c o n t a i n i n g m a n u f a c t u r e r s p a r t n u m b e r . r o 0 0 0 1 0 0 - lxt974a 000101 - lxt975a 3.3:0 manufacturers revision number 4 bits containing manufacturers revision number. ro 0000 1. ro = read only a b c r s x organizationally unique identifier 1 2 3 18 19 24 phy id register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 phy id register 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 manufacturers revision part number number 5 4 3 2 1 0 3 2 1 0 the level one oui is 00207b hex. 59 lxt974a/lxt975a register definitions table 48: auto negotiation advertisement register (address 4) bit name description type 1 default 4.15 next page not supported. ro 0 4.14 reserved ignore. ro 0 4.13 remote fault 1 = remote fault. 0 = no remote fault. r/w 0 4.12:11 reserved ignore. r/w 0 4.10 pause 1 = pause operation is enabled for full-duplex links. 0 = pause operation is disabled. r/w 0 4.9 100base-t4 1 = 100base-t4 capability is available. 0 = 100base-t4 capability is not available. (the lxt974a/975a does not support 100base-t4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100base-t4 operation. an external 100base-t4 transceiver could be switched in if this capability is desired.) r/w 0 4.8 100base-tx full-duplex 1 = port is 100base-tx full-duplex capable. 0 = port is not 100base-tx full-duplex capable. r/w note 2 4.7 100base-tx 1 = port is 100base-tx capable. 0 = port is not 100base-tx capable. r/w note 3 4.6 10base-t full-duplex 1 = port is 10base-t full-duplex capable. 0 = port is not 10base-t full-duplex capable. r/w note 4 4.5 10base-t 1 = port is 10base-t capable. 0 = port is not 10base-t capable. r/w note 5 4.4:0 selector field, s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-negotiation development. unspecified or reserved combinations should not be transmitted. r/w 00001 1. r/w = read/write ro = read only 2. the default value of bit 4.8 is determined by fde anded with cfg_2. 3. the default value of bit 4.7 is determined by cfg_2. 4. the default value of bit 4.6 is determined by fde anded with cfg_1. 5. the default value of bit 4.5 is determined by cfg_1. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 60 table 49: auto negotiation link partner ability register (address 5) bit name description type 1 default 5.15 next page 1 = link partner has ability to send multiple pages. 0 = link partner has no ability to send multiple pages. ro n/a 5.14 acknowledge 1 = link partner has received link code word from lxt974a/ 975a. 0 = link partner has not received link code word from the lxt974a/975a. ro n/a 5.13 remote fault 1 = remote fault. 0 = no remote fault. ro n/a 5.12:11 reserved ignore. ro n/a 5.10 pause 1 = pause operation is enabled for link partner. 0 = pause operation is disabled. ro n/a 5.9 100base-t4 1 = link partner is 100base-t4 capable. 0 = link partner is not 100base-t4 capable. ro n/a 5.8 100base-tx full-duplex 1 = link partner is 100base-tx full-duplex capable. 0 = link partner is not 100base-tx full-duplex capable. ro n/a 5.7 100base-tx 1 = link partner is 100base-tx capable. 0 = link partner is not 100base-tx capable. ro n/a 5.6 10base-t full-duplex 1 = link partner is 10base-t full-duplex capable. 0 = link partner is not 10base-t full-duplex capable. ro n/a 5.5 10base-t 1 = link partner is 10base-t capable. 0 = link partner is not 10base-t capable. ro n/a 5.4:0 selector field s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-negotiation development. unspecified or reserved combinations shall not be transmitted. ro n/a 1. ro = read only 61 lxt974a/lxt975a register definitions table 50: auto negotiation expansion (address 6) bit name description type 1 default 6.15:5 reserved ignore on read. ro 0 6.4 parallel detection fault 1 = parallel detection fault has occurred. 0 = parallel detection fault has not occurred. ro/ lh 0 6.3 link partner next page able 1 = link partner is next page able. 0 = link partner is not next page able. ro 0 6.2 next page able not supported. ro 0 6.1 page received 1 = three identical and consecutive link code words have been received from link partner. 0 = three identical and consecutive link code words have not been received from link partner. ro lh 0 6.0 link partner a/n able 1 = link partner is auto-negotiation able. 0 = link partner is not auto-negotiation able. ro 0 1. ro = read only lh = latching high lxt974a/lxt975a fast ethernet 10/100 quad transceiver 62 table 51: led configuration register (address 16, hex 10) bit name description type 1 default 16.15:12 user defined no effect on chip operation. r/w n/a 16.11:9 reserved ignore on read. ro n/a 16.8 tx pulse tun- ing 1 = faster rise time - may be used to adjust output pulse to match magnetic performance. 0 = normal operation - provides best match for most magnetics. r/w 0 16.7:6 led_2 select determine condition indicated by led_2 r/w 0 0 bit 7 bit 6 indication setting 0 0 led n _2 indicates link 0 1 led n _2 indicates half-duplex status 1 0 led n _2 indicates 100 mbps 1 1 led n _2 indicates collision 16.5:4 led_1 select determine condition indicated by led_1 r/w 0 0 bit 5 bit 4 indication setting 0 0 led n _1 indicates receive activity 0 1 led n _1 indicates link 1 0 led n _1 indicates half-duplex status 1 1 led n _1 indicates 100 mbps 16.3:2 led_0 select determine condition indicated by led_0 r/w 0 0 bit 3 bit 2 indication setting 0 0 led n _0 indicates transmit activity 0 1 led n _0 indicates receive activity 1 0 led n _0 indicates link 1 1 led n _0 indicates half-duplex status 16.1 link algorithm 1 = enhanced link algorithm - link goes down when 12 idle symbols in a row are not received within 1 to 2 ms. 0 = standard link algorithm - link goes down when symbol error rate is greater than 64/1024. r/w 0 16.0 led extension 1 = disable extension of led active time for led n _<2:0>. 0 = enable extension of led active time for led n _<2:0>. r/w 0 1. r/w = read /write 63 lxt974a/lxt975a register definitions table 52: interrupt enable register (address 17, hex 11) bit name description type 1 default 17.15:2 reserved write as 0; ignore on read. r/w n/a 17.1 inten 1 = enable interrupts. must be enabled for bit 17.0 or 19.12 to be effective. 0 = disable interrupts. r/w 0 17.0 tint 1 = forces mdint low and sets bit 18.15 = 1. also forces interrupt pulse on mdio when bit 19.12 = 1. 0 = normal operation. this bit is ignored unless the interrupt function is enabled (17.1 = 1). r/w 0 1. r/w = read /write table 53: interrupt status register (address 18, hex 12) bit name description type 1 default 18.15 mint 1 = indicates mii interrupt pending. 0 = indicates no mii interrupt pending. this bit is cleared by reading register 1 followed by reading register 18. ro n/a 18.14:0 reserved ignore ro 0 1. ro = read only lxt974a/lxt975a fast ethernet 10/100 quad transceiver 64 table 54: port configuration register (address 19, hex 13) bit name description type 1 default 19.15 reserved write as 0; ignore on read. r/w n/a 19.14 txmit test enable (100basetx) 1 = 100base-t transmit test enabled (port will transmit data regard- less of receive status). 0 = normal operation. r/w 0 19.13 reserved write as 0; ignore on read. r/w n/a 19.12 mdio_int 1 = enable interrupt signaling on mdio (if 17.1 = 1). 0 = normal operation (mdio interrupt disabled). bit is ignored unless the interrupt function is enabled (17.1 = 1). r/w 0 19.11 tp loopback enable (10base-t) 1 = disable 10bt loopback - data transmitted by the mac will not loopback to the rxd and rx_dv pins. only crs is looped back. 0 = enable 10bt loopback - preamble, sfd, and data are directly looped back to the mii. r/w 0 19.10 sqe disable (10base-t) 1 = normal operation (sqe enabled). 0 = disable sqe. r/w 0 19.9 jabber disable (10base-t) 1 = disable jabber. 0 = normal operation (jabber enabled). r/w 0 19.8 link test enable (10base-t) 1 = disable 10base-t link integrity test. 0 = normal operation (10base-t link integrity test enabled). r/w note 2 19.7:6 reserved write as 0; ignore on read. r/w n/a 19.5 advance tx clock 1 = tx clock is advanced relative to txd<3:0> and tx_er by 1/2 tx_clk cycle. 0 = normal operation. r/w 0 19.4 reserved write as 0; ignore on read. r/w n/a 19.3 scrambler bypass (100base-t only) 1 = bypass transmit scrambler and receive descrambler. 0 = normal operation (scrambler and descrambler enabled). r/w note 3 19.2 100base-fx 1 = enable 100base fiber interface. 0 = enable 100base twisted pair interface. r/w note 4 19.1 reserved write as 0; ignore on read. r/w 0 19.0 transmit disconnect 1 = disconnect tp transmitter from line. 0 = normal operation. r/w 0 1. r/w = read/write 2. if auto-negotiation is disabled, the default value of bit 19.8 is determined by pin 115 (cfg_1). if cfg_1 is high, the defa ult value of bit 19.8 = 1. if cfg_1 is low, the default value of bit 19.8 = 0. if auto-negotiation is enabled, the default value of bit 19.8 = 0. 3. the default value of bit 19.3 is determined by bypscr. if bypscr is high, the default value of bit 19.3 = 1. if bypscr is low, the default value of bit 19.3 = 0. 4. the default value of bit 19.2 is determined by the sd/tp n pin for the respective port. if sd/tp n is tied low, the default value of bit 19.2 = 0. if sd/tp n is not tied low, the default value of bit 19.2 = 1. on the lxt975a, this bit is ignored on ports 0 and 2 that operate in twisted-pair mode only. 65 lxt974a/lxt975a register definitions table 55: port status register (address 20, hex 14) bit name description type 1 default 20.15:14 reserved write as 0, ignore on read. r/w n/a 20.13 link 1 = link is up. 0 = link is down. link bit 20.13 is a duplicate of bit 1.2, except that it is a dynamic indication, whereas bit 1.2 latches low. ro 0 20.12 duplex mode 1 = full-duplex. 0 = half-duplex. ro note 2 20.11 speed 1 = 100 mbps operation. 0 = 10 mbps operation. ro note 2 20.10 reserved ignore. ro/lh n/a 20.9 auto- negotiation complete 1 = auto-negotiation process complete. 0 = auto-negotiation process not complete. auto-negotiation complete bit 20.9 is a duplicate of bit 1.5. ro/lh 0 20.8 page received 1 = three identical and consecutive link code words received. 0 = three identical and consecutive link code words not received. page received bit 20.8 is a duplicate of bit 6.1. ro/lh 0 20:7 reserved write as 0, ignore on read. r/w 0 20.6 stream cipher lock (100base-tx only) 1 = stream cipher locked. 0 = stream cipher not locked. ro 0 20.5 symbol error 1 = symbol error detected. 0 = no symbol error detected. ro/ lh n/a 20.4 mlt3 encoding error 1 = mlt3 encoding error detected. 0 = no mlt3 encoding error detected. ro/ lh n/a 20.3 reserved ignore. ro n/a 20.2 low-voltage fault 1 = low-voltage fault on vcc has occurred. 0 = no fault. ro/ lh n/a 20.1 reserved write as 0, ignore on read. r/w n/a 20.0 reserved ignore. ro/ lh n/a 1. r/w = read /write ro = read only lh = latching high 2. bits 20.12 and 20.11 reflect the current operating mode of the lxt974a/975a. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 66 package specification figure 40: lxt974a/975a package specification e / 2 e d d 1 e e 1 all dimensions in millimeters a 1 a 2 a 0 - 7 0.13/0.30 r. o b m 12/16 8 places o 0 min. o l 1.60 ref. 0.40 min. 0.13 r. min. - h - - c - notes: 1. all dimensions are in millimeters. 2. this package conforms to jedec publication 95 registration ms-022, variation dd-1. 3. datum plane -h- located at mold parting line and is coincident with leads where leads exit plastic body at bottom of parting line. 4. measured at seating plane -c-. 5. measured at datum plane -h-. 6. dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.254 mm. 7. package top dimensions are smaller than bottom dimensions. top of package will not overhang bottom of package. 8. dimension b does not include dambar protrusion. allowable dambar protrusion is no more than 0.08 mm. quad flat package dim. all dimensions in millimeters min. typ. max. notes a --- 3.70 4.07 a 1 0.25 0.33 --- a 2 3.20 3.37 3.60 d 31.20 bsc 5 d 1 28.00 bsc 6, 7, 8 e 31.20 bsc 5 e 1 28.00 bsc 6, 7, 8 l 0.73 0.88 1.03 m --- --- --- b0.22 --- 0.38 8 e0.65 bsc 160-pin pqfp with heat spreader ? (commercial temp 0 - 70 o c) ? part number lxt974ahc ? part number lxt975ahc ? part number LXT974QC ? part number lxt975qc 67 lxt974a/lxt975a revision history revision history table 56: changes from revision 1.2 to revision 1.3 section page change text tables 22 & 23 magnetic manufacturers 34 update delete tables 22 and 23 and re-number all subsequent tables. refer to application note 73, magnetic manufacturers cross reference guide. figure 32 10base-t jabber 51 update correct col signal assert duration (t2) in the figure only. table 51 led configurations 62 update change register 16, bits 11:9 to reserved and read only. table 57: changes from revision 1.1 to revision 1.2 section page change text all all update change product part numbers from lxt974 and lxt975 to lxt974a and lxt975a. tables 50 and 51 a/n advertisement & link partner ability 60, 61 update add pause capability to registers 4.10 and 5.10. tables 34, 36, 38 transmit timing 47, 49, 51 update change txd<3:0>, tx_en, tx_er hold time (2 ns) min to (0 ns) min. figure 22 typical tp interface & supply filtering 39 update delete alternate 400 w termination circuitry. lxt974a/lxt975a fast ethernet 10/100 quad transceiver 68 table 58: changes from revision 1.0 to revision 1.1 section page change text general description and features 1 update add heat spreader and lxt974ahc and lxt975ahc to the data sheet. add feature bullet, 100base-tx line performance >130 meters. clarify temp range by adding ambient to text. table 1 - 974 sd/tp signal descriptions table 4 975 sd/tp signal descriptions 5 & 7 update delete, the sd/tp n pins have internal pull-downs and will default to global configuration... move listed hardware control pins to tp select section. introduction 14 update change line performance from up to 100 meters to greater than 130 meters. enhanced magnetic mode 15 update delete enhanced magnetic mode discussion to magnetics information section. transmit clock 16 update add master and advanced clock discussion. loopback 17 update add operational loopback and test loopback discussion. add table 13 (test loopback operation) and renumber all subsequent tables. add figure 6 (loopback paths) and renumber all subsequent figures. table 17 configuration without auto-negotiation 20 update simplify notes 3 and 5. figure 12 100base-tx data flow 23 update correct note 2. scrambler can be bypassed setting (19.3 = 1) pwr supply filtering ground filtering layout considerations 31 & 32 update rewrite pwr filtering and pwr/gnd plane layout considerations. replace ground filtering discussion with ground noise. (remove placement of ferrite beads from the ground plane layout recommendations. correct min current rating from 750 ma to 500 ma and bead recommendation to 750 ma. add first bullet to general design guidelines, fill in unused areas of signal planes with solid copper... twisted-pair if 33 update add bullet, improve emi performance by filtering the output centertap and modify relationship to ground plane. 69 lxt974a/lxt975a revision history magnetics information 34 update note 1 - remove enhanced and replace with improved return loss performance. change min return loss for improved magnetics @ 80 mhz from -16 db to -15 db. tables 22 and 23 magnetic manufacturers 35 update remove belfuse part numbers s558-5999-h2, h3, h4, and h5 (enhanced magnetics). remove enhanced footnote from halo magnetics and tg110-s422nx and -s462nx devices. add delta devices; lf8713, lf8701, and lf8251d(enhanced). change note 1 from enhanced to magnetics with improved return loss. figure 20 pwr/gnd connections 38 update remove ground bead and change planes to analog and dig- ital supply planes only. figure 22 typical tp if and supply filtering 39 update correct twisted-pair to rj45 connections in layout diagram for improved magnetics. remove note 1 (common mode chokes) and note 3. add ferrite bead to output centertap and note 2. change enhanced to with improved return loss performance. table 25 operating conditions 42 update change power-down current from 5.0 to 3.0 ma max and add 0.5 ma typical. add 100base-fx max icc - 500 ma. tables 26 and 27 digital i/o charac. digital i/o charac.- mii 43 update change input current from 10 m a to 100 m a. table 30 100base-tx 44 update add 100tx jitter parameters, (0.7 ns typical) and (1.4 ns max). table 34 100base-tx transmit timing 47 update add typical hold spec (-1 ns). change crs on from 3 bt to 2bt typ. change crs off from 4 bt to 3 bt typ. change tx latency from 10 bt to 9 bt. table 36 100base-fx transmit timing 49 update add typical hold spec (-1 ns). change crs on from 3 bt to 2bt typ. change crs off from 4 bt to 3 bt typ. table 37 10base-t rec timing 50 update change footnote 2 from: rxd/rx_dv are not driven during preamble and sfd (64 bt). to: rxd/rx_dv are driven at the start of sfd. table 58: changes from revision 1.0 to revision 1.1 section page change text lxt974a/lxt975a fast ethernet 10/100 quad transceiver 70 table 38 10base-t transmit timing 51 update add typical hold spec (-1 ns). change hold time (5 ns) min to (2 ns) min. change crs on from 0 bt to 2 bt typ. change crs off from 8 bt to 8-11 bt typ. table 42 mii timing 54 update change mdio delay typ from 10 ns to 27 ns. table 46 control register 57 update correct note 2 - when sd_txn is tied high, bit 0.12 = 0. when sd_txn is tied low, bit 0.12 is determined by autoena. table 44 serial led timing 55 update change serial led specs from 10/20 ns to 5/15 ns min and 15/24 ns to 12/21 ns typical. table 53 led configuration reg 63 update change register name to tx pulse tuning and description. table 54 interrupt enable reg 64 update bit 17.1 - remove text, enable half/full-duplex indica- tions on pin 98 and add disable interrupts. table 56 port configuration reg 65 update correct note 3 - if bypscr is high, bit 19.3 = 1. if bypscr is low, bit 19.3 = 0. figure 40 package specification 67 update add heat spreader and ordering information to package diagram. various - edit various minor editing. table 58: changes from revision 1.0 to revision 1.1 section page change text 71 lxt974a/lxt975a notes notes east west asia/pacific europe eastern area headquarters & northeastern regional office western area headquarters asia / pacific area headquarters european area headquarters 234 littleton road, unit 1a westford, ma 01886 tel: (508) 692-1193 fax: (508) 692-1244 3375 scott blvd., #338 santa clara, ca 95054 tel: (408) 496-1950 fax: (408) 496-1955 101 thomson road united square #08-01 singapore 307591 tel: +65 353 6722 fax: +65 353 6711 parc technopolis - bat. zeta 3, avenue du canada - z.a. de courtaboeuf 91974 les ulis cedex france tel: +33 1 64 86 2828 fax: +33 1 60 92 0608 north central regional office south central regional office central asia/pacific regional office central and southern europe regional office one pierce place suite 500e itasca, il 60143 tel: (630) 250-6044 fax: (630) 250-6045 2340 e. trinity mills road suite 306 carrollton, tx 75006 tel: (972) 418-2956 fax: (972) 418-2985 suite 305, 4f-3, no. 75, hsin tai wu road sec. 1, hsi-chih, taipei county, taiwan tel: +886 22 698 2525 fax: +886 22 698 3017 regus feringastrasse 6 d-85774 muenchen- unterfoerhring, germany tel: +49 89 99 216 375 fax: +49 89 99 216 377 southeastern regional office southwestern regional office northern asia/pacific regional office northern europe regional office 4020 westchase blvd raleigh, nc 27615 tel: (919) 836-9798 fax: (919) 836-9818 28203 cabot road suite 300 laguna niguel, ca 92677 tel: (714) 365-5655 fax: (714) 365-5653 nishi-shinjuku, mizuma building 8f 3-3-13, nishi-shinjuku, shinjuku-ku tokyo, 160 japan tel: +81 3 3347-8630 fax: +81 3 3347-8635 torshamnsgatan 35 164/40 kista/stockholm, sweden tel: +46 8 750 3980 fax: +46 8 750 3982 latin/south america 9750 goethe road sacramento, ca 95827 usa tel: (916) 855-5000 fax: (916) 854-1102 revision date status 1.3 11/98 delete magnetic manufacturers tables and change register 16.11:9 to reserved and read only. correct col signal for 10base-t jab timing. international the americas corporate headquarters 9750 goethe road sacramento, california 95827 telephone: (916) 855-5000 fax: (916) 854-1101 web: www.level1.com copyright ? 1999 level one communications, inc., an intel company. specifications subject to change without notice. all rights reserved. printed in the united states of america. pds-t974a/975a-r1.3-1198 the products listed in this publication are covered by one or more of the following patents. additional patents pending. 5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746; 5,166,635; 5,181,228; 5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,267,746; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341; 5,671,249; 5,666,129; 5,701,099 |
Price & Availability of LXT974QC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |